From patchwork Mon Mar 25 08:34:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161040 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696755jan; Mon, 25 Mar 2019 01:37:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqwXzWGACtA2CZTpNwMP7YK43RK8hatNJE46bKiQ9e6Nk05iW3nyq48J7Igk95GYVReExIc3 X-Received: by 2002:a17:902:4101:: with SMTP id e1mr24537229pld.25.1553503050311; Mon, 25 Mar 2019 01:37:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503050; cv=none; d=google.com; s=arc-20160816; b=gCr5lf/cWBuqjHAg3UQKyeyiita+A8ejuoiTDfQAVwyRvfZGnRSJTJ2yQWWqbGxa7P El+tZl3nuCqZKI0/TaQex1jyaznQkvLYlvGN7tpB6VlGtOTfe+GsRTztwjMmzMz3F/Pd t9YGvr+ohn/0Ba9z068xHhf6lE3MUXCj9BFxudSwIuTVZae/+uPHho2lSOJqowEpEsU0 /CXosOU0o8Tch3ygUAa19R2SxRY9Zfc2ZZN3GVlu0hW//TUSOfbh/v6OJLfOi50dibIr Pi1Fc2P60estJpR2hjYKlKvKT8n7JvJnBVDJB1+IEPrsWodD5ctK5JdZHn71/NJmwejh a/fg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=chMDM1S73N5348Ke4wiey3wF6sgdC3UveRlW6BwAUuY=; b=T0NjYptwVNAOoEZUdpqve5rrLk29JJ3VHiDg12rpd/ICztqaX/Rx5YdoHX22j+MCmE 0RcOOK4kq9Zm+eFdWbreTjG3X176djpjto9DDqQC9mfb0APQTixnyv398SDurVJ6kzbQ 7Br1Fki+QLV+3qY0kHKtAO+SXzdfwwe18zMqXJa7OAtUFrbwZew46hEHpN7K56/9dAe5 s5y62A/HMqHkoeTe/paIIn8Fn/9LG/CfxQJqLSIpIraiopLkKSVyAigeIXsaRkdTWQan ij0ag7xwH2n+85cA6hrfLgF8XBOaQx9e3U4LvYtu8ek9UE2x7ie3xU1Y9TffMyTMILr2 eDKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Ke9kO7Mr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g4si12669079pgs.579.2019.03.25.01.37.30; Mon, 25 Mar 2019 01:37:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Ke9kO7Mr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729985AbfCYIh2 (ORCPT + 31 others); Mon, 25 Mar 2019 04:37:28 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:36682 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730323AbfCYIhY (ORCPT ); Mon, 25 Mar 2019 04:37:24 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8bBjV039834; Mon, 25 Mar 2019 03:37:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553503031; bh=chMDM1S73N5348Ke4wiey3wF6sgdC3UveRlW6BwAUuY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Ke9kO7MrjIUhvbMmukZbWdEHyvEo7M3LIS+G7eg0BaR0QBDlF0PonhhK8+xZClZzx 24oWqUPuyTU4GwFQllys/7ZWLRmmfjwTmoynfxyliQkvqKiUWGP93cIh5m2SPgx5ZK vdw9ae3vGe/D3k7lFm+f7135VhOXn+bG4eWplxCQ= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8bBNN089549 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:37:11 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:37:11 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:37:11 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFx006534; Mon, 25 Mar 2019 03:37:07 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 17/26] PCI: keystone: Add support to set the max link speed from DT Date: Mon, 25 Mar 2019 14:04:52 +0530 Message-ID: <20190325083501.8088-18-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PCIe in TI's AM654 devices is by default configured to work in GEN3 mode. However PCIe doesn't work reliably in GEN3 mode because of SERDES configuration. Add support to set the link speed to GEN1, GEN2 or GEN3 based on "max-link-speed" dt property with GEN2 as the default speed if "max-link-speed" is absent. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index e4a816f53b8e..312fd0c49bbb 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -28,6 +28,7 @@ #include #include +#include "../../pci.h" #include "pcie-designware.h" #define PCIE_VENDORID_MASK 0xffff @@ -89,6 +90,8 @@ #define LEG_EP 0x1 #define RC 0x2 +#define EXP_CAP_ID_OFFSET 0x70 + #define KS_PCIE_SYSCLOCKOUTEN BIT(0) #define AM654_PCIE_DEV_TYPE_MASK 0x3 @@ -971,6 +974,31 @@ static int ks_pcie_am654_set_mode(struct device *dev) return 0; } +static void ks_pcie_set_link_speed(struct dw_pcie *pci, int link_speed) +{ + u32 val; + + dw_pcie_dbi_ro_wr_en(pci); + + val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP); + if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) { + val &= ~((u32)PCI_EXP_LNKCAP_SLS); + val |= link_speed; + dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP, + val); + } + + val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2); + if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) { + val &= ~((u32)PCI_EXP_LNKCAP_SLS); + val |= link_speed; + dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2, + val); + } + + dw_pcie_dbi_ro_wr_dis(pci); +} + static const struct ks_pcie_of_data ks_pcie_rc_of_data = { .host_ops = &ks_pcie_host_ops, .version = 0x365A, @@ -1011,6 +1039,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) void __iomem *base; u32 num_viewport; struct phy **phy; + int link_speed; u32 num_lanes; char name[10]; int ret; @@ -1165,6 +1194,12 @@ static int __init ks_pcie_probe(struct platform_device *pdev) gpiod_set_value_cansleep(gpiod, 1); } + link_speed = of_pci_get_max_link_speed(np); + if (link_speed < 0) + link_speed = 2; + + ks_pcie_set_link_speed(pci, link_speed); + pci->pp.ops = host_ops; ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0)