From patchwork Mon Mar 25 08:34:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161039 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696709jan; Mon, 25 Mar 2019 01:37:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqxaXymuEuXZbqnpOvQ0ceOwKjBT9r9FbdneXXJX6HMi/Db9mlJHUSP37V+IOOTyTR9eSBpe X-Received: by 2002:a17:902:d715:: with SMTP id w21mr22836856ply.14.1553503046396; Mon, 25 Mar 2019 01:37:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503046; cv=none; d=google.com; s=arc-20160816; b=mqYu5+2sYXedo4pYVwj8E+YKaOYsbJEaJj/gENkfJTw9KOoN6b0+T4wWetN+pZw9fn bm1vjoBatEKFja8HGhurNFvetII3ekRaD+nuKULymmTvlzHa6fdYDCf83GuVvxQRWnQk 1qlB9cIczaYv/dG4+0rT3iiRMmOFKgJ64TrOPTKcspAo5om+QIzopexScTYBgb1QfX3Y /NO1H6b7aF+SI/dqhbcDxjBmpUhXca01v3emBB8iPcGFTr9twxCoFaBR58G5uxgbICZd r7B+gDpJ5KgG5CgnKp1qP3ysr/FAWKjU55bOXJFp8XucOnFRw54GacndUmHce9gMxbMe J5hQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Z5FsYHz2+eCaWuP/Fr5+/R+9oCvd7mzmcItqNVxbMQU=; b=Fuec3iSFfJnr2d20XkAr49f4plxUIAs6NqS0t76o+LgGuodVIWJI2OmIZKnb2c+S7h Lt6hbWMi9ERTw0oIqg4HkHfkNRi7Ca28bHBdPGNd5tEo48ag0bocfDbf2KHuBQKb8ZYW 2nVCH75dKy3fwAmQIEVLERk8aC6e9biqlUbbfpdZ0Knu6+0tWvIV1WSy85J+/jSeEmHP yp/etnon6k5QMInM5GdZHVfFfF8MFgEErAojdNAR4IBxF0NEzLITNDV1nLrLSBPzSd/A Nm1ZXWmO8SS6K2i5TI3Pv9cdx4j9Wpmqqi1J3NZfi3L8QX0vKVmI2z7uzIs9nOpJ8cc1 KjoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gJQ+yQEX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g4si12669079pgs.579.2019.03.25.01.37.26; Mon, 25 Mar 2019 01:37:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gJQ+yQEX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730325AbfCYIhY (ORCPT + 31 others); Mon, 25 Mar 2019 04:37:24 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:33998 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730289AbfCYIhW (ORCPT ); Mon, 25 Mar 2019 04:37:22 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8ajCH030863; Mon, 25 Mar 2019 03:36:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553503005; bh=Z5FsYHz2+eCaWuP/Fr5+/R+9oCvd7mzmcItqNVxbMQU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gJQ+yQEXu9b9udaGcXG/OL3a15kiZaOfNPDu/VsuhsuN6DIQKF95A4ZvkeBHbwcj4 CMMO1rzAXxQv3TpHNKOyoNXCjEWuAyJRgfqKl8B4YuHmXjwt9PixjFrFCgT1pWnXZl 0QUHwk+cx+rnM/yv9NWELUBCtGYJ7jt6dY1W/6mU= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8ajHU088947 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:36:45 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:36:45 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:36:45 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFr006534; Mon, 25 Mar 2019 03:36:41 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 11/26] PCI: dwc: Fix ATU identification for designware version >= 4.80 Date: Mon, 25 Mar 2019 14:04:46 +0530 Message-ID: <20190325083501.8088-12-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Synopsys designware version >= 4.80 uses a separate register space for programming ATU. The current code identifies if there exists a separate register space by accessing the register address of ATUs in designware version < 4.80. Accessing this address results in abort in the case of K2G. Fix it here by adding "version" member to struct dw_pcie. This should be set by platform specific drivers and designware core will use it to identify if the platform has a separate ATU space. For platforms which hasn't populated the version member, the old method of identification will still be used. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware.c | 14 ++++++++------ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 9 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index a14ca00f72aa..4e2f7946da89 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -358,13 +358,15 @@ void dw_pcie_setup(struct dw_pcie *pci) struct device *dev = pci->dev; struct device_node *np = dev->of_node; - /* Get iATU unroll support */ - pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); - dev_dbg(pci->dev, "iATU unroll: %s\n", - pci->iatu_unroll_enabled ? "enabled" : "disabled"); + if (pci->version >= 0x480A || (!pci->version && + dw_pcie_iatu_unroll_enabled(pci))) { + pci->iatu_unroll_enabled = true; + if (!pci->atu_base) + pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; + } + dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? + "enabled" : "disabled"); - if (pci->iatu_unroll_enabled && !pci->atu_base) - pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; ret = of_property_read_u32(np, "num-lanes", &lanes); if (ret) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index ca3a3190a6f5..90a5b1215344 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -234,6 +234,7 @@ struct dw_pcie { struct pcie_port pp; struct dw_pcie_ep ep; const struct dw_pcie_ops *ops; + unsigned int version; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)