From patchwork Thu Mar 21 23:05:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 160830 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp140195jan; Thu, 21 Mar 2019 16:06:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqwR88ePm5ZvDtzGg8gzEey+nb9TiqPANxVJMVilEm9/q9KjrzliK61q0LcQhpwVIwRj+WWM X-Received: by 2002:a65:620e:: with SMTP id d14mr5848725pgv.28.1553209593384; Thu, 21 Mar 2019 16:06:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553209593; cv=none; d=google.com; s=arc-20160816; b=vAI6z99TIPImL5L8lO+svGQiC+sv3tHFkys1IijFAcn4mTOiCbPnSUP9sYOXhrpk19 ZGa96wFr7gdv+9jIji0OfTH3kMpEXHGLyKuAU8e/el0hQIyaqsTzzCqBHgS46xLxS2Z7 bm4HDb58Mo2sodB2ePwvrIxOMSaayQy8KLLptW9nZP/yr7L6E5S/PhwoJO9ZSsT299TH HxrT0HA8qTBmVT/mDZG5Guih4f3L2o9ufQ0ZJul320656fXh3ciQILVSJRDWb4xlMNAO pHNK3cMCeUdd+HnfvyefLbvyVCUotw9xY1/ssZawkrP6OmynSg0Pu7M60aDpLPgdTeC2 TDEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=eyLtrQWZPhW5bnKOLUtSwNBCjbJQXj1banrSKvaIE2o=; b=taR8QK+gMeZDGAxmhBAoSYaArxHnJFT+4L11LAE4HWKpMcf45xtCxz/H+M/Vcd9I3o pgWsnaMl8TOlWsTFFQ2/OBB4QG+J7xIaond1UkxYLeTCA06cPLuFk4zBK3bRhOoeeN2e 7uI3V+pubvkVZtKvoawwOsKD3y1VFiaCx6vXtooJO6oteLhXgsfjCcBj8QYFnt0DWG5Q IYY1QcXlKYpxe9U3RufSprAcuYdc8GcldpjPb0vnNebCEvZ8uQITDvMwLxPegamUN0Oy KPhNSyegrteqmkN/1OiBuXBSiO90lJLHd0DQYloEb2GBET2/4jW5qjJikNWps4qr7ztw B4sQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id cw2si5953154plb.283.2019.03.21.16.06.32; Thu, 21 Mar 2019 16:06:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727516AbfCUXG0 (ORCPT + 31 others); Thu, 21 Mar 2019 19:06:26 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:35814 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727481AbfCUXGW (ORCPT ); Thu, 21 Mar 2019 19:06:22 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 94173EBD; Thu, 21 Mar 2019 16:06:21 -0700 (PDT) Received: from beelzebub.austin.arm.com (mammon-tx2.austin.arm.com [10.118.29.246]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E29563F614; Thu, 21 Mar 2019 16:06:20 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2e.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton , Andre Przywara , Stefan Wahren Subject: [PATCH v6 08/10] arm64: Always enable ssb vulnerability detection Date: Thu, 21 Mar 2019 18:05:55 -0500 Message-Id: <20190321230557.45107-9-jeremy.linton@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190321230557.45107-1-jeremy.linton@arm.com> References: <20190321230557.45107-1-jeremy.linton@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ssb detection logic is necessary regardless of whether the vulnerability mitigation code is built into the kernel. Break it out so that the CONFIG option only controls the mitigation logic and not the vulnerability detection. Signed-off-by: Jeremy Linton Reviewed-by: Andre Przywara Tested-by: Stefan Wahren --- arch/arm64/include/asm/cpufeature.h | 4 ---- arch/arm64/kernel/cpu_errata.c | 11 +++++++---- 2 files changed, 7 insertions(+), 8 deletions(-) -- 2.20.1 diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index e505e1fbd2b9..6ccdc97e5d6a 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -638,11 +638,7 @@ static inline int arm64_get_ssbd_state(void) #endif } -#ifdef CONFIG_ARM64_SSBD void arm64_set_ssbd_mitigation(bool state); -#else -static inline void arm64_set_ssbd_mitigation(bool state) {} -#endif extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index fb8eb6c6088f..6958dcdabf7d 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -275,7 +275,6 @@ static int detect_harden_bp_fw(void) return 1; } -#ifdef CONFIG_ARM64_SSBD DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required); int ssbd_state __read_mostly = ARM64_SSBD_KERNEL; @@ -346,6 +345,7 @@ void __init arm64_enable_wa2_handling(struct alt_instr *alt, *updptr = cpu_to_le32(aarch64_insn_gen_nop()); } +#ifdef CONFIG_ARM64_SSBD void arm64_set_ssbd_mitigation(bool state) { if (this_cpu_has_cap(ARM64_SSBS)) { @@ -370,6 +370,12 @@ void arm64_set_ssbd_mitigation(bool state) break; } } +#else +void arm64_set_ssbd_mitigation(bool state) +{ + pr_info_once("SSBD disabled by kernel configuration\n"); +} +#endif /* CONFIG_ARM64_SSBD */ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, int scope) @@ -467,7 +473,6 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, return required; } -#endif /* CONFIG_ARM64_SSBD */ static void __maybe_unused cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) @@ -759,14 +764,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors), }, #endif -#ifdef CONFIG_ARM64_SSBD { .desc = "Speculative Store Bypass Disable", .capability = ARM64_SSBD, .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, .matches = has_ssbd_mitigation, }, -#endif #ifdef CONFIG_ARM64_ERRATUM_1188873 { /* Cortex-A76 r0p0 to r2p0 */