From patchwork Thu Mar 21 16:36:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 160811 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1002626jan; Thu, 21 Mar 2019 09:37:43 -0700 (PDT) X-Google-Smtp-Source: APXvYqwQUubnFunu4N5L46wpcFHpfADsUj+QeDtb7KUM4jIw41dG9XJ0Nx74VGpiKKpSSmPVOk7X X-Received: by 2002:a63:c118:: with SMTP id w24mr4152491pgf.67.1553186263191; Thu, 21 Mar 2019 09:37:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553186263; cv=none; d=google.com; s=arc-20160816; b=r8hsqETe0nUsY23bfyIOTGk11m2IMoli1MXJIqf/kPBFIY4eQBeRnPzDKnxbXQFy9i THhRkcH5CtP8eLx02je+o6TRfYv9m428McpOp5kPSvMs6Idd9VJ+KSCRA8P3glwue0zH YlTFJT2SqhKicsSONIC1MJwI0WBfid1+W6aOF4K9G1JttVkVz5nM3334PM7E/OQw/X27 4m+n2p7kxBP5CLspcBSo+cWrOEZIRmRrGKpd3oHG1qorZa9kFv8tZS3pYIDnoU7nuPIq G47P6hE9AQDN7h0sSmWQJecYjXkU3l/GnpRi88+QM5DL0/aNKRXZLuq2okYmERBwCVG1 cwtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=hx8c8qP/KK6vveYXjZp1m60x7qSl3p+e7n9LS4wIjI8=; b=L/j5GnArgGzMROd+CCW+LpcF+kCfhonfSWakh4mfc+vPuwNUN640CDhxRH64z3ecaY iNU4yayKkME1UTltl9Ac9SN3wyQ6R0Clnk0LE8xuvRpVA8UZgafwq/cilap895TxbAjG DrdYnx7AkuBSOU28ZWAymeyifV/W6gR0+xrq5yDsLKyPLVpV7/vIby6sERpN28491FXH OvaM+BVrdz2wR7nXotYb4qqusX5Z1geoUniztKZVp4VdUNOmE2RiqMXHAk280UW6WFNS HxwRf5J6J/xtn24eutiTHZYZSVivHl0fwSvzwu5qnfnr4TmNabz86ISlVrn09dGwyVEf iWZA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x14si4777895pgq.185.2019.03.21.09.37.42; Thu, 21 Mar 2019 09:37:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728550AbfCUQhl (ORCPT + 31 others); Thu, 21 Mar 2019 12:37:41 -0400 Received: from foss.arm.com ([217.140.101.70]:59442 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728690AbfCUQg6 (ORCPT ); Thu, 21 Mar 2019 12:36:58 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 57347EBD; Thu, 21 Mar 2019 09:36:58 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 675413F614; Thu, 21 Mar 2019 09:36:56 -0700 (PDT) From: Julien Grall To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu Cc: christoffer.dall@arm.com, james.morse@arm.com, marc.zyngier@arm.com, julien.thierry@arm.com, suzuki.poulose@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, Julien Grall Subject: [PATCH RFC 08/14] arm64/mm: Split asid_inits in 2 parts Date: Thu, 21 Mar 2019 16:36:17 +0000 Message-Id: <20190321163623.20219-9-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190321163623.20219-1-julien.grall@arm.com> References: <20190321163623.20219-1-julien.grall@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Move out the common initialization of the ASID allocator in a separate function. Signed-off-by: Julien Grall --- arch/arm64/mm/context.c | 43 +++++++++++++++++++++++++++++++------------ 1 file changed, 31 insertions(+), 12 deletions(-) -- 2.11.0 diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index fb13bc249951..b071a1b3469e 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -271,31 +271,50 @@ asmlinkage void post_ttbr_update_workaround(void) CONFIG_CAVIUM_ERRATUM_27456)); } -static int asids_init(void) +/* + * Initialize the ASID allocator + * + * @info: Pointer to the asid allocator structure + * @bits: Number of ASIDs available + * @asid_per_ctxt: Number of ASIDs to allocate per-context. ASIDs are + * allocated contiguously for a given context. This value should be a power of + * 2. + */ +static int asid_allocator_init(struct asid_info *info, + u32 bits, unsigned int asid_per_ctxt) { - struct asid_info *info = &asid_info; - - info->bits = get_cpu_asid_bits(); - info->ctxt_shift = ilog2(ASID_PER_CONTEXT); + info->bits = bits; + info->ctxt_shift = ilog2(asid_per_ctxt); /* * Expect allocation after rollover to fail if we don't have at least - * one more ASID than CPUs. ASID #0 is reserved for init_mm. + * one more ASID than CPUs. ASID #0 is always reserved. */ WARN_ON(NUM_CTXT_ASIDS(info) - 1 <= num_possible_cpus()); atomic64_set(&info->generation, ASID_FIRST_VERSION(info)); info->map = kcalloc(BITS_TO_LONGS(NUM_CTXT_ASIDS(info)), sizeof(*info->map), GFP_KERNEL); if (!info->map) - panic("Failed to allocate bitmap for %lu ASIDs\n", - NUM_CTXT_ASIDS(info)); - - info->active = &active_asids; - info->reserved = &reserved_asids; + return -ENOMEM; raw_spin_lock_init(&info->lock); + return 0; +} + +static int asids_init(void) +{ + u32 bits = get_cpu_asid_bits(); + + if (!asid_allocator_init(&asid_info, bits, ASID_PER_CONTEXT)) + panic("Unable to initialize ASID allocator for %lu ASIDs\n", + 1UL << bits); + + asid_info.active = &active_asids; + asid_info.reserved = &reserved_asids; + pr_info("ASID allocator initialised with %lu entries\n", - NUM_CTXT_ASIDS(info)); + NUM_CTXT_ASIDS(&asid_info)); + return 0; } early_initcall(asids_init);