From patchwork Thu Mar 21 16:36:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 160802 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1001854jan; Thu, 21 Mar 2019 09:36:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqy8Wd7xDNgmGD6HZqT3ryVdt2ImTyBV9xe1r4zOCRvkW7IKkQgcY+qDcpCecgAFVgFQalO1 X-Received: by 2002:a63:1723:: with SMTP id x35mr4069726pgl.364.1553186216819; Thu, 21 Mar 2019 09:36:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553186216; cv=none; d=google.com; s=arc-20160816; b=SWjRAqdL1IdTgMVKK/p0oM7hOAGdU2nXiFG6ng5FAmeXzSQ4zblBib43c/QQDlbJLA Ot+tK26eAjNAySCGS0R6yqNbIaiEnKMpzLa4idmtWy4dRnyAEFiZeLku7mCdoTbOY0On JgViby81m8v6fOzstX+1a/nOjv/vBD1noZmx6pbVjRwENpSsubYq9dkMKFj56Yca0JNB C1ra8IAU2u4AMzKIoYwoi4XG5XWT4WPMZgF9EMSTESOPDPbhdVonCyO2S/GWK+vqmkjj C+8c5voyQ4I+BjAHNqYjQr1MWmdirCh0cNOyqp2PJeiyOYGDO4Vzh1OrH8sFUceTytob 1E4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=AUEhiB1OdB9Pd+vTlmH/pmARc0jMnn/mnjtHblH1WWo=; b=uF7H/7ZAiFYj0t1WEJFQnYRZT6CDwa1zsXSFmxskpPW6Hmf/qSwsXq3eu6IOkEgCQd Rw3h5GilCFXg+TuMXmMSv8vy4nIg7upY54bBb128xLzAa4l+D7JD5JnlQL9ydgVReyhw 3fM5zKWZqDBm9vdRb5zxPoLDbaG1hGsGMjcLjDCLJbMd6mgkh8iSPx/F92AwlUeH/g1U 18oixHnKHeLcqNWVzrrX/aEIs0hy1CxufnV4toC6EBUafkrcDzKGF2gFfqrkraY8u5U6 aTYrWZHgYBM0twuQp7yxel3PSGahHnDPFKNRv9a9KNCtkqLFahv3dGEXYJ6N/b06495j 6PXg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p24si3231726pfd.288.2019.03.21.09.36.56; Thu, 21 Mar 2019 09:36:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728663AbfCUQgy (ORCPT + 31 others); Thu, 21 Mar 2019 12:36:54 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:59386 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728649AbfCUQgt (ORCPT ); Thu, 21 Mar 2019 12:36:49 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 93A41EBD; Thu, 21 Mar 2019 09:36:49 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 805B93F614; Thu, 21 Mar 2019 09:36:47 -0700 (PDT) From: Julien Grall To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu Cc: christoffer.dall@arm.com, james.morse@arm.com, marc.zyngier@arm.com, julien.thierry@arm.com, suzuki.poulose@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, Julien Grall , Julien Grall Subject: [PATCH RFC 04/14] arm64/mm: Move the variable lock and tlb_flush_pending to asid_info Date: Thu, 21 Mar 2019 16:36:13 +0000 Message-Id: <20190321163623.20219-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190321163623.20219-1-julien.grall@arm.com> References: <20190321163623.20219-1-julien.grall@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The variables lock and tlb_flush_pending holds information for a given ASID allocator. So move them to the asid_info structure. Signed-off-by: Julien Grall --- arch/arm64/mm/context.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) -- 2.11.0 diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index da17ed6c7117..e98ab348b9cb 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -27,8 +27,6 @@ #include #include -static DEFINE_RAW_SPINLOCK(cpu_asid_lock); - struct asid_info { atomic64_t generation; @@ -36,6 +34,9 @@ struct asid_info atomic64_t __percpu *active; u64 __percpu *reserved; u32 bits; + raw_spinlock_t lock; + /* Which CPU requires context flush on next call */ + cpumask_t flush_pending; } asid_info; #define active_asid(info, cpu) *per_cpu_ptr((info)->active, cpu) @@ -44,8 +45,6 @@ struct asid_info static DEFINE_PER_CPU(atomic64_t, active_asids); static DEFINE_PER_CPU(u64, reserved_asids); -static cpumask_t tlb_flush_pending; - #define ASID_MASK(info) (~GENMASK((info)->bits - 1, 0)) #define ASID_FIRST_VERSION(info) (1UL << ((info)->bits)) @@ -124,7 +123,7 @@ static void flush_context(struct asid_info *info) * Queue a TLB invalidation for each CPU to perform on next * context-switch */ - cpumask_setall(&tlb_flush_pending); + cpumask_setall(&info->flush_pending); } static bool check_update_reserved_asid(struct asid_info *info, u64 asid, @@ -233,7 +232,7 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) old_active_asid, asid)) goto switch_mm_fastpath; - raw_spin_lock_irqsave(&cpu_asid_lock, flags); + raw_spin_lock_irqsave(&info->lock, flags); /* Check that our ASID belongs to the current generation. */ asid = atomic64_read(&mm->context.id); if ((asid ^ atomic64_read(&info->generation)) >> info->bits) { @@ -241,11 +240,11 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) atomic64_set(&mm->context.id, asid); } - if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) + if (cpumask_test_and_clear_cpu(cpu, &info->flush_pending)) local_flush_tlb_all(); atomic64_set(&active_asid(info, cpu), asid); - raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); + raw_spin_unlock_irqrestore(&info->lock, flags); switch_mm_fastpath: @@ -288,6 +287,8 @@ static int asids_init(void) info->active = &active_asids; info->reserved = &reserved_asids; + raw_spin_lock_init(&info->lock); + pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS(info)); return 0;