From patchwork Thu Mar 21 16:36:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 160805 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1002012jan; Thu, 21 Mar 2019 09:37:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqwoXHtcUgTzH/T6rSaK+IIVz+1N3fav5jLYiVlx7qk4pZpGWIWUtAzKBzgSY/gMgEU/9jC3 X-Received: by 2002:a65:6259:: with SMTP id q25mr4204969pgv.235.1553186225760; Thu, 21 Mar 2019 09:37:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553186225; cv=none; d=google.com; s=arc-20160816; b=GipjXTK9ninvH1oc6Rlz0ZSbcu9UGHSIC8dd/poATGHW/GxdtJMAR11rL/rDJYX84P G0lsdCOqbE/jWZ1TzUR58Lij9hiV+ovB62+0qSKjLIBbUQMrtgHAYmztxOt/oSHftR1O ou73JUIyQX719izeHsPA+x6mrD/eoI3T5MCC7ja9SoRzPZuREAPhPJ5cCTdEnyVND0Kl /rrejEBzL+xR9/O1dNd7Q3B9tota/yKSEeuWnZPuOtSFCTcqQeq2MhU3JlU72GsUlvMr WJ6S+QvK2QcK0FF+JW7tNUJMDkA+rkjMbpv96T0KlCnpQnizRUX5BhSu5jLxoqV0brXb witw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=0z61gpWptVb8W6OIzZg5rilVW6cMGsq224JUxoSaKs4=; b=c9rdYeRHohfH8zVpepLpCNRncsINqlCT/sIKBCTnHwEZX2cl0bQSKSBMQ9jooa15nK 4ceHXLflAXGSQ+ClWG631qfiC9x0iQnpyRlJuznMNlU4NBhdV9XIQE3hUe5tbv2rVZ3V 747z0lJUXhfI2iFjL2Ms6VFIBtQBvTtWDh7iW3oPXbvOlx6coX3DrtlqRhlBgR6Sh+zo LUiI7LvFUhi/T0e4ilDQzaqHNQ+VFJFstNeRBRqj4AwaiCev9RWqX9v2D34pHXOlNpwd i0V1K4SjlevbxpaHNc0xIIMmr+h+nZctOA1u0704bVhrsp+BoxbAOJygE3e2AQ3RhAa3 KrsA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p3si821984pgr.382.2019.03.21.09.37.05; Thu, 21 Mar 2019 09:37:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728710AbfCUQhD (ORCPT + 31 others); Thu, 21 Mar 2019 12:37:03 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:59454 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727987AbfCUQhB (ORCPT ); Thu, 21 Mar 2019 12:37:01 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 85651374; Thu, 21 Mar 2019 09:37:00 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 958113F614; Thu, 21 Mar 2019 09:36:58 -0700 (PDT) From: Julien Grall To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu Cc: christoffer.dall@arm.com, james.morse@arm.com, marc.zyngier@arm.com, julien.thierry@arm.com, suzuki.poulose@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, Julien Grall Subject: [PATCH RFC 09/14] arm64/mm: Split the function check_and_switch_context in 3 parts Date: Thu, 21 Mar 2019 16:36:18 +0000 Message-Id: <20190321163623.20219-10-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190321163623.20219-1-julien.grall@arm.com> References: <20190321163623.20219-1-julien.grall@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The function check_and_switch_context is used to: 1) Check whether the ASID is still valid 2) Generate a new one if it is not valid 3) Switch the context While the latter is specific to the MM subsystem, the rest could be part of the generic ASID allocator. After this patch, the function is now split in 3 parts which corresponds to the use of the functions: 1) asid_check_context: Check if the ASID is still valid 2) asid_new_context: Generate a new ASID for the context 3) check_and_switch_context: Call 1) and 2) and switch the context 1) and 2) have not been merged in a single function because we want to avoid to add a branch in when the ASID is still valid. This will matter when the code will be moved in separate file later on as 1) will reside in the header as a static inline function. Signed-off-by: Julien Grall --- Will wants to avoid to add a branch when the ASID is still valid. So 1) and 2) are in separates function. The former will move to a new header and make static inline. --- arch/arm64/mm/context.c | 51 +++++++++++++++++++++++++++++++++++++------------ 1 file changed, 39 insertions(+), 12 deletions(-) -- 2.11.0 diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index b071a1b3469e..cbf1c24cb3ee 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -204,16 +204,21 @@ static u64 new_context(struct asid_info *info, atomic64_t *pasid) return idx2asid(info, asid) | generation; } -void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) +static void asid_new_context(struct asid_info *info, atomic64_t *pasid, + unsigned int cpu); + +/* + * Check the ASID is still valid for the context. If not generate a new ASID. + * + * @pasid: Pointer to the current ASID batch + * @cpu: current CPU ID. Must have been acquired throught get_cpu() + */ +static void asid_check_context(struct asid_info *info, + atomic64_t *pasid, unsigned int cpu) { - unsigned long flags; u64 asid, old_active_asid; - struct asid_info *info = &asid_info; - if (system_supports_cnp()) - cpu_set_reserved_ttbr0(); - - asid = atomic64_read(&mm->context.id); + asid = atomic64_read(pasid); /* * The memory ordering here is subtle. @@ -234,14 +239,30 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) !((asid ^ atomic64_read(&info->generation)) >> info->bits) && atomic64_cmpxchg_relaxed(&active_asid(info, cpu), old_active_asid, asid)) - goto switch_mm_fastpath; + return; + + asid_new_context(info, pasid, cpu); +} + +/* + * Generate a new ASID for the context. + * + * @pasid: Pointer to the current ASID batch allocated. It will be updated + * with the new ASID batch. + * @cpu: current CPU ID. Must have been acquired through get_cpu() + */ +static void asid_new_context(struct asid_info *info, atomic64_t *pasid, + unsigned int cpu) +{ + unsigned long flags; + u64 asid; raw_spin_lock_irqsave(&info->lock, flags); /* Check that our ASID belongs to the current generation. */ - asid = atomic64_read(&mm->context.id); + asid = atomic64_read(pasid); if ((asid ^ atomic64_read(&info->generation)) >> info->bits) { - asid = new_context(info, &mm->context.id); - atomic64_set(&mm->context.id, asid); + asid = new_context(info, pasid); + atomic64_set(pasid, asid); } if (cpumask_test_and_clear_cpu(cpu, &info->flush_pending)) @@ -249,8 +270,14 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) atomic64_set(&active_asid(info, cpu), asid); raw_spin_unlock_irqrestore(&info->lock, flags); +} + +void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) +{ + if (system_supports_cnp()) + cpu_set_reserved_ttbr0(); -switch_mm_fastpath: + asid_check_context(&asid_info, &mm->context.id, cpu); arm64_apply_bp_hardening();