From patchwork Wed Feb 27 01:05:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 159252 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp3851805jad; Tue, 26 Feb 2019 17:06:26 -0800 (PST) X-Google-Smtp-Source: AHgI3IanamRYIkiWn0kWdFcGI7TdsoY5PkmvY21gLTMeHfQVttfvv02CJSHvhXbxM7CI2/dvsH7d X-Received: by 2002:a65:6294:: with SMTP id f20mr335038pgv.174.1551229586713; Tue, 26 Feb 2019 17:06:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551229586; cv=none; d=google.com; s=arc-20160816; b=dwakIJ0L+b5RWJ11iPLmouqLTgsTwyZ4uuJdwpVIyUajmXLlYMvTkqCytErZ14OMn8 sODjwaN4FQU6+hXh4OE28DhHZBaF8o1scFTMfrRA/9cAjJj5vqXIpnAYlNg8PB9b+lbh sUkCunVpbfjC4t2RZZ5PM6ReJFoUOjczMBOWBzL63wtPilqVvQo4VJEKMss5tEctYRh0 34mmFf4+qViuNVStIrHSgzYyqUBV8a4Vco+DsRDOufrO61C3BnTYsOWhMl7KWRrpDXmS YnDRr24moYwfCC46RVgGdaFtVfHVa9zfRxNh7zZlchdLxgxrKSzRBdjOSr9x2bsH2CWo sOmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=o/SlX8GwP6cqPa1kuJHcBkWplEHk+7HEkeYTTmFOUhY=; b=bWdtHQTBGJ3H7lYQ+6NSzIwWv0Ahv0JYFrdodjAiAECx2fhtQbfTCOG7CJYRcBHUj2 ZuGeW4zBxSG3h5NPFwbdOuHEezHudqRetpqFNGOM+eFxiZaM2vU4rs4f8e7lxvv3zDTr WuBuMOzIFnoEUsrWkzNoLV2/dPg8AeVpiCbBuhnJfJl7znlDwf0bkpt01sYk4hVpNj3A N/DwRz5YaMejrWKz+LwjfWhOhaiHFgBnYfJEd03k46sExJabtYB8C6DhvlZwCdvt9n/6 IrBYFCoTmrrGyAC1gdmZbOhYmWKX6yndKQW5qsBW1Iv8PzOpOUjR3B2PggAFvh0gQzFG SblQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a6si13664738pgc.137.2019.02.26.17.06.26; Tue, 26 Feb 2019 17:06:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729641AbfB0BGY (ORCPT + 31 others); Tue, 26 Feb 2019 20:06:24 -0500 Received: from foss.arm.com ([217.140.101.70]:55682 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729574AbfB0BGK (ORCPT ); Tue, 26 Feb 2019 20:06:10 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 38EE01A25; Tue, 26 Feb 2019 17:06:10 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9A28D3F5C1; Tue, 26 Feb 2019 17:06:09 -0800 (PST) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2e.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v5 08/10] arm64: Always enable ssb vulnerability detection Date: Tue, 26 Feb 2019 19:05:42 -0600 Message-Id: <20190227010544.597579-9-jeremy.linton@arm.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190227010544.597579-1-jeremy.linton@arm.com> References: <20190227010544.597579-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ssb detection logic is necessary regardless of whether the vulnerability mitigation code is built into the kernel. Break it out so that the CONFIG option only controls the mitigation logic and not the vulnerability detection. Signed-off-by: Jeremy Linton --- arch/arm64/include/asm/cpufeature.h | 4 ---- arch/arm64/kernel/cpu_errata.c | 11 +++++++---- 2 files changed, 7 insertions(+), 8 deletions(-) -- 2.20.1 Reviewed-by: Andre Przywara diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index dfcfba725d72..c2b60a021437 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -628,11 +628,7 @@ static inline int arm64_get_ssbd_state(void) #endif } -#ifdef CONFIG_ARM64_SSBD void arm64_set_ssbd_mitigation(bool state); -#else -static inline void arm64_set_ssbd_mitigation(bool state) {} -#endif extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 0f6e8f5d67bc..5f5611d17dc1 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -276,7 +276,6 @@ static int detect_harden_bp_fw(void) return 1; } -#ifdef CONFIG_ARM64_SSBD DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required); int ssbd_state __read_mostly = ARM64_SSBD_KERNEL; @@ -347,6 +346,7 @@ void __init arm64_enable_wa2_handling(struct alt_instr *alt, *updptr = cpu_to_le32(aarch64_insn_gen_nop()); } +#ifdef CONFIG_ARM64_SSBD void arm64_set_ssbd_mitigation(bool state) { if (this_cpu_has_cap(ARM64_SSBS)) { @@ -371,6 +371,12 @@ void arm64_set_ssbd_mitigation(bool state) break; } } +#else +void arm64_set_ssbd_mitigation(bool state) +{ + pr_info_once("SSBD, disabled by kernel configuration\n"); +} +#endif /* CONFIG_ARM64_SSBD */ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, int scope) @@ -468,7 +474,6 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, return required; } -#endif /* CONFIG_ARM64_SSBD */ static void __maybe_unused cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) @@ -760,14 +765,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors), }, #endif -#ifdef CONFIG_ARM64_SSBD { .desc = "Speculative Store Bypass Disable", .capability = ARM64_SSBD, .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, .matches = has_ssbd_mitigation, }, -#endif #ifdef CONFIG_ARM64_ERRATUM_1188873 { /* Cortex-A76 r0p0 to r2p0 */