From patchwork Wed Feb 27 01:05:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 159249 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp3851600jad; Tue, 26 Feb 2019 17:06:14 -0800 (PST) X-Google-Smtp-Source: AHgI3IamK2COYoFvBEs07NovAJQqAXvRavWUg3tqxsIvN8dyA95ajVSCOJhPDNTDBDvdMv4JaReM X-Received: by 2002:a63:6545:: with SMTP id z66mr336138pgb.182.1551229574097; Tue, 26 Feb 2019 17:06:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551229574; cv=none; d=google.com; s=arc-20160816; b=QKcfGh3B5cfm8JLE25d5DWOrGULSJIc1tKtucrpdZVq0sVToHVI5+QyeAscBfJ8+0C 9H6xPcT/yJkWBA9NDjClWCRhrQoz/Y7sgcLVAvkLkXasaaCGZAq2QaWyQ6eeYVKRKmgF XjbuH6LCjlOc1saT7Gyq+vTaXznAYEguOYzt16blhriWlwxY8daWIAyLs45SDKBWEwxJ bbJuCwsb2PklUwDa1Juz8iE6HUePmO5NZv+GR/ASrnDGCNISL6ejDHJ1bArOLRr8WGt6 d5K8XPz9k9rfuRzH/ftEbGOMC1StUGv1m2hDiqTOPthS14KIOj5deJIGmf9PTMkRzq8y hJnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=B4KmVAyBGsNqk96L4NwaeWOrYyawyIIrtKGfDXtk61U=; b=MDERbJOu31/5hg0P7gmydacl2ysHkyzo6PBOYx2lQYu9eMBFeUsfck25T9CKIqFT/q ogdo2xuonjE3bai+rVt2JMdyr5NzEnumSSGUeHm1JUFB9wqm2/fevjBuQAsb1KxQv/Ya 9vTnhDIkZ0KSFwaoEHkDb2FjZ9ayY7nOpIUm3MGePYKSKSZ3cMaCtwdD/2BAVJIZEubp mXNh28cTXA0F8SofAdNb6+mLrwWDHVqntwkMt7tQdBPy/quUdVqXVsQa0zBEEv3Umv1w 18Ho9NOTK76z+e4oYa+HwJyYrhVBqXvF2dDXV0wVHw6I0geluQ/A3lYNjzWAPtdNRZrK amjA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t18si11728444pgv.285.2019.02.26.17.06.12; Tue, 26 Feb 2019 17:06:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729587AbfB0BGL (ORCPT + 31 others); Tue, 26 Feb 2019 20:06:11 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:55654 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729560AbfB0BGI (ORCPT ); Tue, 26 Feb 2019 20:06:08 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E86C619BF; Tue, 26 Feb 2019 17:06:07 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 552CC3F5C1; Tue, 26 Feb 2019 17:06:07 -0800 (PST) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2e.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v5 06/10] arm64: Always enable spectrev2 vulnerability detection Date: Tue, 26 Feb 2019 19:05:40 -0600 Message-Id: <20190227010544.597579-7-jeremy.linton@arm.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190227010544.597579-1-jeremy.linton@arm.com> References: <20190227010544.597579-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The sysfs patches need to display machine vulnerability status regardless of kernel config. Prepare for that by breaking out the vulnerability/mitigation detection code from the logic which implements the mitigation. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cpu_errata.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) -- 2.20.1 Reviewed-by: Andre Przywara diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 77f021e78a28..a27e1ee750e1 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -109,12 +109,12 @@ cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused) atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1); -#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR #include #include DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); + #ifdef CONFIG_KVM_INDIRECT_VECTORS extern char __smccc_workaround_1_smc_start[]; extern char __smccc_workaround_1_smc_end[]; @@ -270,11 +270,11 @@ static int detect_harden_bp_fw(void) ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)) cb = qcom_link_stack_sanitization; - install_bp_hardening_cb(cb, smccc_start, smccc_end); + if (IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR)) + install_bp_hardening_cb(cb, smccc_start, smccc_end); return 1; } -#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ #ifdef CONFIG_ARM64_SSBD DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required); @@ -513,7 +513,6 @@ cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ CAP_MIDR_RANGE_LIST(midr_list) -#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR /* * List of CPUs that do not need any Spectre-v2 mitigation at all. */ @@ -545,6 +544,11 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope) if (!need_wa) return false; + if (!IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR)) { + pr_warn_once("spectrev2 mitigation disabled by configuration\n"); + return false; + } + /* forced off */ if (__nospectre_v2) { pr_info_once("spectrev2 mitigation disabled by command line option\n"); @@ -557,8 +561,6 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope) return (need_wa > 0); } -#endif - #ifdef CONFIG_HARDEN_EL2_VECTORS static const struct midr_range arm64_harden_el2_vectors[] = { @@ -732,13 +734,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), }, #endif -#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, .matches = check_branch_predictor, }, -#endif #ifdef CONFIG_HARDEN_EL2_VECTORS { .desc = "EL2 vector hardening",