From patchwork Thu Feb 21 10:15:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 158898 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp311372jaa; Thu, 21 Feb 2019 02:20:39 -0800 (PST) X-Google-Smtp-Source: AHgI3IYliaDyPycwFcj3jTgGYkUuzZAGn/17UBiFPNnpuXaCbiGB8VtDf944xO7d7Cr10yaHRTzu X-Received: by 2002:a17:902:7405:: with SMTP id g5mr32294831pll.230.1550744439627; Thu, 21 Feb 2019 02:20:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550744439; cv=none; d=google.com; s=arc-20160816; b=DmaUoRdK2RmbZEHPMyyrAqJL8pn10By+Z8K7alOL53aJ7+TD6gTZnmpYixhoy0GIY4 3Tw6AZbWG53fm7aJsAm6Dj1L+hIq7h1aZuxn1KQJQdXvoygcDUyg+/R4LmhD4G0/sHAZ HTxDHpG3Uv/Mcb8CnhMpvhjI5D0HW1XJocLqMyqpU37DGzO1rgiq8SbSizRna1qPTVrc AxcppNsBNYKpQBdzlxNPbKAhoHsz+hSsXbZgwjdz2ywt2eo7iH+ydhfCNcEvJ1KRPTzP Tya6/2pS3DSBAr3J3mfH1dqc6/x4BBGot3nNTTPGRB3ZMdef1U7aBGdlwoykdLkSryqa E6Mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Go6T+1CivfbPMLGs7e9/cCiN7G9c2oxS2QLNAmkij9s=; b=hyrT25+hJ0wkaZyXUWt11JpE578EmbTfIGa3hk9nEhLOxDrWUBC3/zQKKASlVKJp9t JjqN0UfVsSYg745RKfK4UsK39vzmI5fbD2sISe+sf6mgfB+qndQ8UHh8jW/6zHwZo9ja UeiZmDzaRxwCynMCqC2RWT3ic6XzgV2yqDv44eVccagj8qbM2qSLPytvUN39+K5D5ni1 O9GerMClr9ERt/lRHdv/XSzsXA1S9YD7ug79fBak7HLZMAoiiLbwHbXp2oNmD6/5uI7R jHP5AZcbnyt/NV4jcCumVquLoOvvE0W1wz/+nHeY4Xkd0cMwU2d8qMlfiTsnoLpPbXiH Rm+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=EFuR3qVN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e40si22466205plb.234.2019.02.21.02.20.39; Thu, 21 Feb 2019 02:20:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=EFuR3qVN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727894AbfBUKS5 (ORCPT + 32 others); Thu, 21 Feb 2019 05:18:57 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:42126 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727828AbfBUKSy (ORCPT ); Thu, 21 Feb 2019 05:18:54 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x1LAIjM7053208; Thu, 21 Feb 2019 04:18:45 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1550744325; bh=Go6T+1CivfbPMLGs7e9/cCiN7G9c2oxS2QLNAmkij9s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EFuR3qVN31FKhHzSvE3M+xFx75b6q8Op9WmIy/zY77I2iyiKx6Mo4v+jk21YtUrf4 rEO/hKFyqSr+2rO5gN5qBvsktmOn7Arqz9tDLVGCDa98MzMIUZAWjWURD+327THkX5 Y1c09IpuELeRDdyaO7XbMWxuSjZ2mKhsJk0GZRGM= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x1LAIjVA052879 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 21 Feb 2019 04:18:45 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 21 Feb 2019 04:18:44 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 21 Feb 2019 04:18:44 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x1LAIORL022198; Thu, 21 Feb 2019 04:18:42 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , , , Subject: [PATCH v4 6/9] PCI: dwc: Add support to use non default msi_irq_chip Date: Thu, 21 Feb 2019 15:45:15 +0530 Message-ID: <20190221101518.22604-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190221101518.22604-1-kishon@ti.com> References: <20190221101518.22604-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Platforms using DesignWare IP use dw_pci_msi_bottom_irq_chip for configuring the MSI controller logic within the DesignWare IP. However certain platforms like Keystone (K2G) which uses DesignWare IP have their own MSI controller logic. For handling such platforms, the irqchip ops use msi_irq_ack(), msi_set_irq(), msi_clear_irq() callback functions. Add support to use different msi_irq_chip with default as dw_pci_msi_bottom_irq_chip. This is in preparation to get rid of msi_irq_ack(), msi_set_irq(), msi_clear_irq() and other Keystone specific dw_pcie_host_ops. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-host.c | 5 ++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 721d60a5d9e4..042de09b0451 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -245,7 +245,7 @@ static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, for (i = 0; i < nr_irqs; i++) irq_domain_set_info(domain, virq + i, bit + i, - &dw_pci_msi_bottom_irq_chip, + pp->msi_irq_chip, pp, handle_edge_irq, NULL, NULL); @@ -277,6 +277,9 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); + if (!pp->msi_irq_chip) + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; + pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, &dw_pcie_msi_domain_ops, pp); if (!pp->irq_domain) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 9943d8c68335..cb6eeb062f47 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -176,6 +176,7 @@ struct pcie_port { struct irq_domain *irq_domain; struct irq_domain *msi_domain; dma_addr_t msi_data; + struct irq_chip *msi_irq_chip; u32 num_vectors; u32 irq_status[MAX_MSI_CTRLS]; raw_spinlock_t lock;