From patchwork Thu Feb 21 10:15:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 158895 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp310077jaa; Thu, 21 Feb 2019 02:19:13 -0800 (PST) X-Google-Smtp-Source: AHgI3IbsKmFZ6+9IFZ31fdN+NyUDCYqWQ6a+cXd2EoBiF7itOOUsfyjQGBgSv50imjLcEBFnexDQ X-Received: by 2002:a62:1d8f:: with SMTP id d137mr39108361pfd.11.1550744353328; Thu, 21 Feb 2019 02:19:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550744353; cv=none; d=google.com; s=arc-20160816; b=LNfAEUxctfdq39PtMF734FeCFYz4nBZ3Cw6ISivSyi7Ai9M4F13fbfpMcjdSCbuxrK Bg7yhuU42MKTh3YMaEwiUeApunxXqsRQQz/60cUtLwmNjn/Q1FSvQCzrGc2ILOZfKRyC tNV04q6ysRWXD8VMdjKAp8OPGUlhGnSIGToxnFd7U9F6ff3Zs2DokjTK9nmlNfxFTgX7 bnxCBWZ6Jr7357Br8PCZShzt6jm/UMkDPPlEIoB5ctVFG6NDhyFmK4p63il6LUtPVyYQ oiTAQBYRayiapINvp5ShzHDnddALU96Z/lvAuN4QvYL3lYFcvZFV8P0kNgt8gLXmnCj5 y9yA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=fAqNlTR7cMaMsca9ZKERwJ2A9RfxaY/X8QU7ZLjB4i0=; b=AP4VbxjwxZR7qZlvvhq+LDw1rZqDYy1BdAE8TmpSt2gnjWsn+Nlyoi8cvKNQOPpG+k VfW+CkZe6fMMC2fl+lTVIqo1TwHZUytQhEZa9WPNd701E58BZf9ys5B8Z0/noglqMQB6 GqXSQ4+QzVVnGY9LNgTOEL+6fJz/FQCYFLd2hBknHDS2sADX4nxZjIfSvtTW67DqWHF3 ews7YStTmG7oTw99QBqqmcb9AilXJDr5myt8IxT/1SP6FKehNl4VWsxZgDw/2Bjtwq1M TQw88bYyju+plvCFDI7/7R66ax9UaQpxeXTYIEZhw4YiW9xbEzeeiYiUw/tz3B0KVpFm Lnkw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jbaKRvdm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b9si21089173plr.66.2019.02.21.02.19.13; Thu, 21 Feb 2019 02:19:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jbaKRvdm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728030AbfBUKTL (ORCPT + 32 others); Thu, 21 Feb 2019 05:19:11 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:48220 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727988AbfBUKTI (ORCPT ); Thu, 21 Feb 2019 05:19:08 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x1LAIrq5124823; Thu, 21 Feb 2019 04:18:53 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1550744333; bh=fAqNlTR7cMaMsca9ZKERwJ2A9RfxaY/X8QU7ZLjB4i0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jbaKRvdmqUw6TDoHPxTqG/H9ocfOLO2+o7X4dtEGQ4zUpgt6FOv3rNSfjG4uShxEv Sc9JIiNMtIRGWaWB94v26nkLqZjjM0I6rcsBa8RyXnAiLKXkIOTaaSV1xhfwNN4Zzs td6Yv5mllm2/nr1POmVbkDdSxApBPDFmJOkgvefU= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x1LAIrMc052999 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 21 Feb 2019 04:18:53 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 21 Feb 2019 04:18:53 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 21 Feb 2019 04:18:53 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x1LAIORO022198; Thu, 21 Feb 2019 04:18:50 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , , , Subject: [PATCH v4 9/9] PCI: dwc: Do not write to MSI control registers if the platform doesn't use it Date: Thu, 21 Feb 2019 15:45:18 +0530 Message-ID: <20190221101518.22604-10-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190221101518.22604-1-kishon@ti.com> References: <20190221101518.22604-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Platforms which populate msi_host_init, has it's own MSI controller logic. Writing to MSI control registers on platforms which doesn't use Designware's MSI controller logic might have side effects. To be safe, do not write to MSI control registers if the platform uses it's own MSI controller logic instead of Designware's MSI controller logic. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/dwc/pcie-designware-host.c | 24 ++++++++++--------- 1 file changed, 13 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 781735f06dea..2bc2fd582124 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -641,17 +641,19 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_setup(pci); - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - - /* Initialize IRQ Status array */ - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, ~0); - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, ~0); - pp->irq_status[ctrl] = 0; + if (!pp->ops->msi_host_init) { + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + /* Initialize IRQ Status array */ + for (ctrl = 0; ctrl < num_ctrls; ctrl++) { + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + 4, ~0); + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + 4, ~0); + pp->irq_status[ctrl] = 0; + } } /* Setup RC BARs */