From patchwork Tue Feb 19 07:54:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 158692 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3377589jaa; Mon, 18 Feb 2019 23:57:16 -0800 (PST) X-Google-Smtp-Source: AHgI3IZUMXAnjWXV2dQ1f0uQywLyDHC0pZyV6nZnij7EuSpLJAmoHTQ83fKgGHu2pAzEWddiDL7/ X-Received: by 2002:a63:29c3:: with SMTP id p186mr22830246pgp.24.1550563036668; Mon, 18 Feb 2019 23:57:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550563036; cv=none; d=google.com; s=arc-20160816; b=TnM9EKFyW2Ei+wT65rIolseb2MZfuzeKxJIQ43KLRT5k57SWtiP1wFfdnwA17SVHHw 1F7ps4zKcsImDwuLOXhKsG/8MModlHtKxj4BryQzBLYqd3tyo7OQLwx3uoxFhkLCS6Iz Os/DGuAp51r5pM/Pxqsk8QlMw7faVbuLDp0rlUQJ1rD7Z6/rvV/icFOvILP85m3/I8I2 GZCB76ezRZC5D1gArp26ZGf+y416fQtXrlHVFA72EMtq8tX93fb352gfavPJ6kxeCvs9 59iktkvkupouD3N/Jy5SMIG3vkrXIe+Q5XEyp1ECDW1Bohc8ny3cPoesuox9H+1hSQkV ig+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=dCUBr31f4Go3Gg7A1z5SiBc0ZELnR1JYG3EU6GZZxYo=; b=ZrTgaTJq8KStYxXeZHvho/qgzL9kdRCzgisQS9t91LLJiU8ZO1/9OmhUbJhvdNwyAD qIRb/82fHUUcPqcK2UjsCa529HIm507iS8giUfLzE8TvLp1sWv9rRtCjrbpZG2YeUvmn fZKLpervCyC13fVeDXzw3Jt497p1eSYYAoaawfo7YDuDFLplBD66ShitmZChU/Kv8HTp syRrJtSDFxDIe9ars0VbsVzvmhP67KTOwQ/UpVDBuKCFvPabp02U7xIqPj+xcjs3LStD tvRUvMc7ahm1oQqimoCXjWCXb1qU5WgHPnSWZNEOUNo3v+lU1iPQOKpi1LdxbRha6SYs aSOw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l7si17032453plb.366.2019.02.18.23.57.16; Mon, 18 Feb 2019 23:57:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727714AbfBSH5P (ORCPT + 32 others); Tue, 19 Feb 2019 02:57:15 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:3783 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725764AbfBSH5K (ORCPT ); Tue, 19 Feb 2019 02:57:10 -0500 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id CE2F61F92350A8F9A9FE; Tue, 19 Feb 2019 15:57:05 +0800 (CST) Received: from HGHY1l002753561.china.huawei.com (10.177.23.164) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.408.0; Tue, 19 Feb 2019 15:56:55 +0800 From: Zhen Lei To: Jean-Philippe Brucker , Robin Murphy , Will Deacon , Joerg Roedel , linux-arm-kernel , iommu , linux-kernel CC: Zhen Lei Subject: [PATCH 1/5] iommu/arm-smmu-v3: make sure the stale caching of L1STD are invalid Date: Tue, 19 Feb 2019 15:54:39 +0800 Message-ID: <20190219075443.17732-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.19.2.windows.1 In-Reply-To: <20190219075443.17732-1-thunder.leizhen@huawei.com> References: <20190219075443.17732-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.164] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Invalidate the caching of the intermediate L1ST descriptor after it has been updated. Signed-off-by: Zhen Lei --- drivers/iommu/arm-smmu-v3.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) -- 1.8.3 diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 0d28402..2072897 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -1072,13 +1072,14 @@ static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu, *dst = cpu_to_le64(val); } -static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) +static void +__arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid, bool leaf) { struct arm_smmu_cmdq_ent cmd = { .opcode = CMDQ_OP_CFGI_STE, .cfgi = { .sid = sid, - .leaf = true, + .leaf = leaf, }, }; @@ -1086,6 +1087,16 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) arm_smmu_cmdq_issue_sync(smmu); } +static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) +{ + __arm_smmu_sync_ste_for_sid(smmu, sid, true); +} + +static void arm_smmu_sync_std_for_sid(struct arm_smmu_device *smmu, u32 sid) +{ + __arm_smmu_sync_ste_for_sid(smmu, sid, false); +} + static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid, __le64 *dst, struct arm_smmu_strtab_ent *ste) { @@ -1233,6 +1244,7 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid) arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT); arm_smmu_write_strtab_l1_desc(strtab, desc); + arm_smmu_sync_std_for_sid(smmu, sid); return 0; }