From patchwork Wed Feb 13 13:26:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 158222 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp71688jaa; Wed, 13 Feb 2019 05:27:57 -0800 (PST) X-Google-Smtp-Source: AHgI3IYoYVLo/h2+ZzvJAyXtSV4FpAUtpS/zasnU/Bd2vgkCsXZGN2vUQIpYO/0t3skjlxrklt66 X-Received: by 2002:a17:902:7c8a:: with SMTP id y10mr524634pll.71.1550064477529; Wed, 13 Feb 2019 05:27:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550064477; cv=none; d=google.com; s=arc-20160816; b=SWk4paY87zxWdvLfse1emOUkvYZ1eAetAbT+1kijsN39E4Rb1aNPVbklgJVinjmC6f eL41R1q1c0Md96ChJtnp2ZZN9J/67HzSPqUlUL1QZoT+LneEDs4jyy2KSA90KC0a4Rin 8fxq5P8dkdRsPTGva/g2tK+376mAPLQfWgDrrkCxsAbw4BNEjHuOXNae6eqdCIjYUs48 z0FMOQXrM6Jwk38REf5JkqI8loC3ooUopyQsvngL4T/+vO2hoeRjuOEQW2DGD/dQJ3tN 8lO0vZ9V3jD+DpdSkIyisSPv5gSOuT5OoYWQYdAYczcXHL2Bx1RoSGa80w1qddwTg6m7 HCfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Go6T+1CivfbPMLGs7e9/cCiN7G9c2oxS2QLNAmkij9s=; b=GM3Ajlp+/+XKYYLIw1bJC9iQCSnncOiOX/2oY7cWRVHPzStuE4A+a3Putev2V+4xNt YBy/Rm/AL57uDrgNvgfz8oBg0S6vggARjcEFhSMaXRWZc+PWRQkR76HZqAVIRM2jnof+ xGArT51s9a+96TNWsqoYgziJHpRKUFTZnBjAvC/BiBNInnqOLZ3wnliS9EevKKgB3dt/ pqIwMnT5gzErbQqKcRRu05TFH7xN0dF+uRnexbewQMEkYB3S4xpA++lsRA34FHluFWK/ q+YqhhTbgwt7XUbXLiUUER+gdZXeR2VtoIZYXxAkIcS3XkfKCkeN605pPYZ2e5Y6wQ5z X+nw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=CYgLadR1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l12si6363048pgm.464.2019.02.13.05.27.57; Wed, 13 Feb 2019 05:27:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=CYgLadR1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391043AbfBMN1z (ORCPT + 31 others); Wed, 13 Feb 2019 08:27:55 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:38444 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727264AbfBMN1x (ORCPT ); Wed, 13 Feb 2019 08:27:53 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x1DDRb8h071661; Wed, 13 Feb 2019 07:27:37 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1550064457; bh=Go6T+1CivfbPMLGs7e9/cCiN7G9c2oxS2QLNAmkij9s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=CYgLadR1QUBl5g6hirnwgb4U9P2VZjdRRf4Czs/K4dOrmiNIQhAhUIVZIO4thjPbJ PpDPFUloM/jHfltnhis2GEq0OntuFHb6Z7dh6FYzgoI6FygqtpHx1nBJjjaMn7M5nJ QVT/Q5jvQc+G0Nmy+4ryl5pgMzocC6IC2HF6PhGs= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x1DDRb5g117513 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 13 Feb 2019 07:27:37 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Wed, 13 Feb 2019 07:27:37 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Wed, 13 Feb 2019 07:27:37 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x1DDRGZg016688; Wed, 13 Feb 2019 07:27:34 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , , , Subject: [PATCH v3 6/9] PCI: dwc: Add support to use non default msi_irq_chip Date: Wed, 13 Feb 2019 18:56:26 +0530 Message-ID: <20190213132629.24790-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190213132629.24790-1-kishon@ti.com> References: <20190213132629.24790-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Platforms using DesignWare IP use dw_pci_msi_bottom_irq_chip for configuring the MSI controller logic within the DesignWare IP. However certain platforms like Keystone (K2G) which uses DesignWare IP have their own MSI controller logic. For handling such platforms, the irqchip ops use msi_irq_ack(), msi_set_irq(), msi_clear_irq() callback functions. Add support to use different msi_irq_chip with default as dw_pci_msi_bottom_irq_chip. This is in preparation to get rid of msi_irq_ack(), msi_set_irq(), msi_clear_irq() and other Keystone specific dw_pcie_host_ops. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-host.c | 5 ++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 721d60a5d9e4..042de09b0451 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -245,7 +245,7 @@ static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, for (i = 0; i < nr_irqs; i++) irq_domain_set_info(domain, virq + i, bit + i, - &dw_pci_msi_bottom_irq_chip, + pp->msi_irq_chip, pp, handle_edge_irq, NULL, NULL); @@ -277,6 +277,9 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); + if (!pp->msi_irq_chip) + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; + pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, &dw_pcie_msi_domain_ops, pp); if (!pp->irq_domain) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 9943d8c68335..cb6eeb062f47 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -176,6 +176,7 @@ struct pcie_port { struct irq_domain *irq_domain; struct irq_domain *msi_domain; dma_addr_t msi_data; + struct irq_chip *msi_irq_chip; u32 num_vectors; u32 irq_status[MAX_MSI_CTRLS]; raw_spinlock_t lock;