From patchwork Wed Feb 13 13:26:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 158225 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp72023jaa; Wed, 13 Feb 2019 05:28:21 -0800 (PST) X-Google-Smtp-Source: AHgI3IbKLaHOfTn23jZT7Go6gjdQV2XU2PTq/9UU3MCoahqiE+21sg+b7K2z45XwPyAfjWDaCNma X-Received: by 2002:a17:902:583:: with SMTP id f3mr579529plf.202.1550064501805; Wed, 13 Feb 2019 05:28:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550064501; cv=none; d=google.com; s=arc-20160816; b=AYqZZUiw35z7aWCGZgU3Mmcu0lTd6w/vog9Hw3bu2EWN0v/ob5uf+DCuec9bQlEb27 9xXPV4nHwd0B0FVpcBuRdbtT1sGaYvrg5GmWlF4jn7mU4RDeiWeSK5SvyVQCHjFhZhAz VrN/NUnpvbe5T+4gF7dk6EFdiebgSjTPr0TNF0aqVG9zqFKFfXqrhnnuljvKoI1mAhFs RR4pP8TEHhFvrBJOcZBhRd6mp2DIYUzZsmu4nHqWSoylkDW2P72eqz3jwHVos+7qQP8x Ijt+ABMlYIfymtNm/HcnUOWQIf/NK5Z3MBU+QyHEUCe2Crc2pCMMiI/UkrTd5xmy9b4o Q6Lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=fAqNlTR7cMaMsca9ZKERwJ2A9RfxaY/X8QU7ZLjB4i0=; b=ddf/0vlymBuyBIKFt3InAGxjN3cWRrgfQ1vP0LWbNF8SwUkfl99ArqEV18QRpMZURF CszeaSaseNOCwdtdr/TEPWPzIzyqTWM4CrKAijRtOhBduWhpGXvE0fZDlnT+OpDerlBj fFnmdOMwnDlkBKHQEMGig2KtVrd1UXJFKwz+NDg6HOhY1Zs9ZWlTpqrbaURaziFaTTq0 l1qwfdEDrV30USWM8yCZIkGVAVLdB6U3jUudRCTIp2Oq/m/x3mZDW/afEdjXBpEXXumE ZSmSodcK5PhGvopR32tj++sSg/9sYJzDv8qFh4H5vSLGVLqkRBjBhFUCl9G6TkKyPahO ms3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rZdhw+Eh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v28si15704265pfa.238.2019.02.13.05.28.21; Wed, 13 Feb 2019 05:28:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rZdhw+Eh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404083AbfBMN2T (ORCPT + 31 others); Wed, 13 Feb 2019 08:28:19 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:38098 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2403799AbfBMN2N (ORCPT ); Wed, 13 Feb 2019 08:28:13 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x1DDRkXX061180; Wed, 13 Feb 2019 07:27:46 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1550064466; bh=fAqNlTR7cMaMsca9ZKERwJ2A9RfxaY/X8QU7ZLjB4i0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rZdhw+EhPKyWX24qFCHvmoYFj/8rTffUYzZZZ8RVfWPdiq7Z3H9tTEvhUz+ujTkq9 fnXjggg0x9AQwsWJvhuYrCcdIAjh13bq2SrYEpmxnO6z8bgo2ZhgogTiRsHe0YBE6+ 1BZ2Fa8LQX5EEHEArar78OuqyC6o97ngv9NVtgKo= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x1DDRkCf025618 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 13 Feb 2019 07:27:46 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Wed, 13 Feb 2019 07:27:46 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Wed, 13 Feb 2019 07:27:45 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x1DDRGZj016688; Wed, 13 Feb 2019 07:27:43 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , , , Subject: [PATCH v3 9/9] PCI: dwc: Do not write to MSI control registers if the platform doesn't use it Date: Wed, 13 Feb 2019 18:56:29 +0530 Message-ID: <20190213132629.24790-10-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190213132629.24790-1-kishon@ti.com> References: <20190213132629.24790-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Platforms which populate msi_host_init, has it's own MSI controller logic. Writing to MSI control registers on platforms which doesn't use Designware's MSI controller logic might have side effects. To be safe, do not write to MSI control registers if the platform uses it's own MSI controller logic instead of Designware's MSI controller logic. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/dwc/pcie-designware-host.c | 24 ++++++++++--------- 1 file changed, 13 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 781735f06dea..2bc2fd582124 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -641,17 +641,19 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_setup(pci); - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - - /* Initialize IRQ Status array */ - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, ~0); - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, ~0); - pp->irq_status[ctrl] = 0; + if (!pp->ops->msi_host_init) { + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + /* Initialize IRQ Status array */ + for (ctrl = 0; ctrl < num_ctrls; ctrl++) { + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + 4, ~0); + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + 4, ~0); + pp->irq_status[ctrl] = 0; + } } /* Setup RC BARs */