From patchwork Thu Feb 7 11:09:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 157708 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp531101jaa; Thu, 7 Feb 2019 03:32:58 -0800 (PST) X-Google-Smtp-Source: AHgI3IaHWji/M07GGEk3N6I3K7PJaYOqyTbYhmGKHLq6nOZTxqP6B0/kzqRQ3zSMlRo3ymEkyG1t X-Received: by 2002:aa7:808f:: with SMTP id v15mr7871851pff.30.1549539178010; Thu, 07 Feb 2019 03:32:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549539178; cv=none; d=google.com; s=arc-20160816; b=w7WUXKzUI7jWPjuC0SD78i4NuEuy8MVdKpAFczq2Kv8av2kFLAtMN1zqhOBCDB+pp9 YTGjS8adgie9oVnQjaCIa3spfjG8TEEQIb1djI9CBYwPT2ubIcuePbsdLOBEdr4j9Odq vhorx/tXJ7W7QUDm+cbX/eFbTsUrQjCugCW8+iRH7MgwhL14qvNTnR/rXgFv/pHv1UIB UQj3IfMjjHHMB+FvqYbWGi4Ud1hKW50CF16etKxO7q0f4wgqi0jiL9Tl5FKcAEc6HC3T gYbcTw4lRdNBK509UvCL9LgSBbEpmCHs+Xu9xdB0KYSywIzTBAkepcbyQ3vVQ9QOfqsr flcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=zM9Td9IPdnQ4poiwQG4NpDYQ8HxesMv3eUNXS4tDPuQ=; b=nAL9r4KEEwkGC2/nMwwaxr332ZZjN6cgc7LtVnqmWH8wlm2ys/iwI1tSv80KD9UgbK bFqQRTPoJbW/DKdNYYydjZYIUuJJFQtgm3PFrD3whiS3vKiTPG0gGOQGaFqOdtkvcnbh eFFKM41Ww5WOpRc/LvEG9h9l4DR8qOtGFj/DhQNDzTyk5dZ7XuHqSl1hd7U8g9IbhAKw 0bmPYxfaRggjr1/SLJEgFXmvxbsX96IMubsrY2sllSWUkB4HlZSuZ+toCkWO/hMaFoBr 6QYaMBXbRe8+1IYmW01tUlELTEHtErHdwyU/fAi6zFeWM1K4+V7hccQ1W+d6pxA+laJA Z5Lg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="E/rOYfLN"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m198si9015065pga.98.2019.02.07.03.32.57; Thu, 07 Feb 2019 03:32:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="E/rOYfLN"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727266AbfBGLcz (ORCPT + 31 others); Thu, 7 Feb 2019 06:32:55 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:53322 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726764AbfBGLcw (ORCPT ); Thu, 7 Feb 2019 06:32:52 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x17BWUmb094530; Thu, 7 Feb 2019 05:32:30 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1549539150; bh=zM9Td9IPdnQ4poiwQG4NpDYQ8HxesMv3eUNXS4tDPuQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=E/rOYfLNiwIP+378pFcSfLSZNuirUeWe1V18HqDNf8oBwvFCwK/raYcj84h2UYonf YrY9BBq2NjbLT0N9C+La+Ljim/ipVsCvd4PxpywBKtIVpcRwdtQFp5GkJOSpURgAol GAi6OCOgSDTHyKroCD5jz5QUuuSfTfXTUVu7OeMI= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x17BWUdD073075 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Feb 2019 05:32:30 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 7 Feb 2019 05:32:30 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 7 Feb 2019 05:32:30 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x17BVxat026282; Thu, 7 Feb 2019 05:32:27 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , , , Subject: [PATCH v2 9/9] PCI: dwc: Do not write to MSI control registers if the platform doesn't use it Date: Thu, 7 Feb 2019 16:39:24 +0530 Message-ID: <20190207110924.30716-10-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190207110924.30716-1-kishon@ti.com> References: <20190207110924.30716-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Platforms which populate msi_host_init, has it's own MSI controller logic. Writing to MSI control registers on platforms which doesn't use Designware's MSI controller logic might have side effects. To be safe, do not write to MSI control registers if the platform uses it's own MSI controller logic instead of Designware's MSI controller logic. Signed-off-by: Kishon Vijay Abraham I Acked-by: Gustavo Pimentel --- .../pci/controller/dwc/pcie-designware-host.c | 24 ++++++++++--------- 1 file changed, 13 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 9492b05e8ff0..d7184e1a7d92 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -647,17 +647,19 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_setup(pci); - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - - /* Initialize IRQ Status array */ - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, ~0); - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, ~0); - pp->irq_status[ctrl] = 0; + if (!pp->ops->msi_host_init) { + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + /* Initialize IRQ Status array */ + for (ctrl = 0; ctrl < num_ctrls; ctrl++) { + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + 4, ~0); + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + 4, ~0); + pp->irq_status[ctrl] = 0; + } } /* Setup RC BARs */