From patchwork Fri Jan 25 23:45:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 156659 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp938268jaa; Fri, 25 Jan 2019 15:45:53 -0800 (PST) X-Google-Smtp-Source: ALg8bN6xhqExF/+MThq4sYVQbdQyHpNQ8szxVSIjSqlrld163RTEYYofhKIUylf3F2lBKQuOhwDY X-Received: by 2002:a17:902:6b87:: with SMTP id p7mr13250153plk.282.1548459953264; Fri, 25 Jan 2019 15:45:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548459953; cv=none; d=google.com; s=arc-20160816; b=Mkf8oUTlzi6VmxTdeID2OSlhU9fLGIy/aET4mNEGE9pZX8PH96D0Glp8J8t8Z4SncK ZwBhUjetHZ3HfZoc2v875l4ti32zNe/wvndVPVB+tzTPAQVPPkKGdyaiVPJ+AThtbI6F YUe/4glUyKphSh8r3NHRcgXw7EhZBcWCBPhuS6qI8oq6k8lEVHOZptjjN1mBlO3Q6hb/ 7zuX3SlUs65yUZAgMXvtpke3J/NmqxRzo+OyYikyqqcenIw6TJ/0jH8OT6QTNcrjPjOk xrCzNaAS+L3vLWOHyBH+TPkx5qdh1P13XYlqzc8gUQocAT7a4S82sb3wssjYNUvIDq7y DF9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=xkiykm+iIdEw+kUjDsxAkLCG9M3FjlogGZBSkl9Jpc8=; b=TwkeVNs2/0jGwUBm3Gwsp4kX+b2GgeNs/gMg6Dy/UCgFI4mZU5GqooNhzeo+Tp1tKN wIgIkH11Ylg4+nrwrA6+Gq9Q7dGZuQO0vZt2iVk/lsWdaugeJ9VDYbNIq4Qo8rOb8BDJ jXqt4nQdZ4Y5eGWo91u2r5flwuse6CxKOLLgHFhJ6EbFZayK4xvcfhVf3wvFJ+4yxliM NpZxbX7WQYj19kIFjxZBdtxNaWZC8Pqn9/f669O6SXaRWSQch6UFGJ+i+WNVEGdhMXHq DhH2qXyTQhKlk2WvYmdmFOhiP818XcnG3Q8WJICbqIHcSm4RGYeQCAhdZIvmzFKRjhgv iMgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Mv2+dkNb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z6si26064946pgl.109.2019.01.25.15.45.52; Fri, 25 Jan 2019 15:45:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Mv2+dkNb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729688AbfAYXpv (ORCPT + 31 others); Fri, 25 Jan 2019 18:45:51 -0500 Received: from mail-pg1-f196.google.com ([209.85.215.196]:44268 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729649AbfAYXps (ORCPT ); Fri, 25 Jan 2019 18:45:48 -0500 Received: by mail-pg1-f196.google.com with SMTP id t13so4810405pgr.11 for ; Fri, 25 Jan 2019 15:45:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xkiykm+iIdEw+kUjDsxAkLCG9M3FjlogGZBSkl9Jpc8=; b=Mv2+dkNbL0k5DvH4k0022xpt2XmaRAc3I/c6yTkAlZO7gKJ9L1CsGKCt5dboV0533Z R0GkYbcpI3KBHaiYUAWvyyBviw84fMv5m12TT23GTWp3SzRW8jBm/hFEZUkWMw73mLjX /uhHkroDHqfm+09j17kps0INpuekC0NcqagDM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xkiykm+iIdEw+kUjDsxAkLCG9M3FjlogGZBSkl9Jpc8=; b=C7v6AMxEWeaXjM7N7750yNxkjZpirzrGJmBAVph1s13nigGX7cLsDPzPOsu6DdINFs iLwkNj1cldcxAOViKUGzXYVoNcZirpvZ6IFTZi3Sfmg4tUc3djtZedI+1e7OAdry+5s9 /ipNjhV5IOZlUjTGA8X4fp9ByXJVu1QDt6Ar0JhSa/k5fM3WVjJ7EJErs0wdGxeAQDY7 xE8rIsFc8m8MW5avSKJFSXAOY3tiAyif0UTUhrp8dVuA6eRiTfGAWA6w/OfgPO/4V8Jj HU3EAk8JzE10tCt+HTLIUdC+lcBnaDut67dPOPHPcUw0fq1ezKvT8fHlBGhqFcFVNino uchg== X-Gm-Message-State: AJcUukdycLeQxeFcRGDdTKpN5Xt/VF5zOhx1EPEtSqMcw77ibGHr3MGU BsdDgrPM/gMPi2lIb2S+hydlEA== X-Received: by 2002:a63:24c2:: with SMTP id k185mr11426478pgk.406.1548459946951; Fri, 25 Jan 2019 15:45:46 -0800 (PST) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id y9sm32950302pfi.74.2019.01.25.15.45.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 Jan 2019 15:45:46 -0800 (PST) From: Bjorn Andersson To: Andy Gross Cc: Bjorn Helgaas , David Brown , Khasim Syed Mohammed , Kishon Vijay Abraham I , Lorenzo Pieralisi , Mark Rutland , Michael Turquette , Niklas Cassel , Rob Herring , Stanimir Varbanov , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 7/7] arm64: dts: qcom: qcs404: Add PCIe related nodes Date: Fri, 25 Jan 2019 15:45:09 -0800 Message-Id: <20190125234509.26419-8-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190125234509.26419-1-bjorn.andersson@linaro.org> References: <20190125234509.26419-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The QCS404 has a PCIe2 PHY and a Qualcomm PCIe controller, add these to the platform dtsi and enable them for the EVB with the perst gpio and analog supplies defined. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 25 +++++++++ arch/arm64/boot/dts/qcom/qcs404.dtsi | 67 ++++++++++++++++++++++++ 2 files changed, 92 insertions(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 50b3589c7f15..579ddaf4f5fa 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -21,6 +21,22 @@ }; }; +&pcie { + status = "ok"; + + perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&perst_state>; +}; + +&pcie_phy { + status = "ok"; + + vdda-vp-supply = <&vreg_l3_1p05>; + vdda-vph-supply = <&vreg_l5_1p8>; +}; + &remoteproc_adsp { status = "ok"; }; @@ -137,6 +153,15 @@ }; &tlmm { + perst_state: perst { + pins = "gpio43"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + output-low; + }; + sdc1_on: sdc1-on { clk { pins = "sdc1_clk"; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 76699435c8bd..7b219865ba7e 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -3,6 +3,7 @@ #include #include +#include / { interrupt-parent = <&intc>; @@ -377,6 +378,7 @@ compatible = "qcom,gcc-qcs404"; reg = <0x01800000 0x80000>; #clock-cells = <1>; + #reset-cells = <1>; assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; assigned-clock-rates = <19200000>; @@ -405,6 +407,21 @@ #interrupt-cells = <4>; }; + pcie_phy: phy@7786000 { + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; + reg = <0x07786000 0xb8>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, + <&gcc GCC_PCIE_0_PIPE_ARES>; + reset-names = "phy", "pipe"; + + clock-output-names = "pcie_0_pipe_clk"; + #phy-cells = <0>; + + status = "disabled"; + }; + sdcc1: sdcc@7804000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, <0x7805000 0x1000>; @@ -771,6 +788,56 @@ status = "disabled"; }; }; + + pcie: pci@10000000 { + compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; + reg = <0x10000000 0xf1d + 0x10000f20 0xa8 + 0x07780000 0x2000 + 0x10001000 0x2000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0 0 0x10003000 0 0x00010000 /* I/O */ + 0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>; + clock-names = "iface", "aux", "master_bus", "slave_bus"; + + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_AHB_ARES>; + reset-names = "axi_m", + "axi_s", + "axi_m_sticky", + "pipe_sticky", + "pwr", + "ahb"; + + phys = <&pcie_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; }; timer {