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[209.132.180.67]) by mx.google.com with ESMTP id n4si99599pgm.487.2019.01.14.03.16.18; Mon, 14 Jan 2019 03:16:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=f3sD6HNC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726759AbfANLQR (ORCPT + 31 others); Mon, 14 Jan 2019 06:16:17 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:45328 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726469AbfANLQP (ORCPT ); Mon, 14 Jan 2019 06:16:15 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EBFtlh112673; Mon, 14 Jan 2019 05:15:55 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547464555; bh=UxFV2AA/OxJ+RGbF6mGrC+ScIM/GAuGJn+bhMgD6qEM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=f3sD6HNCShsAqDvvThjSjSh6ZV9XuUzizQl/De5staAp3gWhblDVfYwrVM1Y0IDdA o1SAZutWn5iPD4M8o4mwKYlYdj6cde9/5AYd6VpmoZfxB5RqDKrOHQEJnHzXuIe8vC 7SygVG2L7ogoCeO1wWEVIMvv5ADDygDOrOcF8Mvw= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EBFtSu107903 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 05:15:55 -0600 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 05:15:55 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 05:15:54 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EBFd1V011560; Mon, 14 Jan 2019 05:15:51 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Lorenzo Pieralisi , Gustavo Pimentel , Alan Douglas , Shawn Lin , Heiko Stuebner CC: Bjorn Helgaas , Jingoo Han , , , , , Subject: [PATCH v2 03/15] PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops Date: Mon, 14 Jan 2019 16:45:01 +0530 Message-ID: <20190114111513.21618-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114111513.21618-1-kishon@ti.com> References: <20190114111513.21618-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Populate ->get_features() dw_pcie_ep_ops to return the EPC features supported by Designware PCIe endpoint controller. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-plat.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index c12bf794d69c..bd0516afc86f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -100,9 +100,22 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, return 0; } +static const struct pci_epc_features dw_plat_pcie_epc_features = { + .linkup_notifier = false, + .msi_capable = true, + .msix_capable = true, +}; + +static const struct pci_epc_features* +dw_plat_pcie_get_features(struct dw_pcie_ep *ep) +{ + return &dw_plat_pcie_epc_features; +} + static struct dw_pcie_ep_ops pcie_ep_ops = { .ep_init = dw_plat_pcie_ep_init, .raise_irq = dw_plat_pcie_ep_raise_irq, + .get_features = dw_plat_pcie_get_features, }; static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,