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McKenney" To: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, mingo@kernel.org Cc: stern@rowland.harvard.edu, parri.andrea@gmail.com, will.deacon@arm.com, peterz@infradead.org, boqun.feng@gmail.com, npiggin@gmail.com, dhowells@redhat.com, j.alglave@ucl.ac.uk, luc.maranget@inria.fr, willy@infradead.org, Benjamin Herrenschmidt , Arnd Bergmann , David Laight , linux-doc@vger.kernel.org, "Paul E . McKenney" Subject: [PATCH RFC LKMM 5/7] docs/memory-barriers.txt: Enforce heavy ordering for port I/O accesses Date: Wed, 9 Jan 2019 13:07:46 -0800 X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190109210706.GA27268@linux.ibm.com> References: <20190109210706.GA27268@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19010921-0052-0000-0000-00000375B341 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00010374; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000274; SDB=6.01144138; UDB=6.00595704; IPR=6.00924400; MB=3.00025055; MTD=3.00000008; XFM=3.00000015; UTC=2019-01-09 21:07:55 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19010921-0053-0000-0000-00005F6789E0 Message-Id: <20190109210748.29074-5-paulmck@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-09_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=963 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901090168 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Will Deacon David Laight explains: | A long time ago there was a document from Intel that said that | inb/outb weren't necessarily synchronised wrt memory accesses. | (Might be P-pro era). However no processors actually behaved that | way and more recent docs say that inb/outb are fully ordered. This also reflects the situation on other architectures, the the port accessor macros tend to be implemented in terms of readX/writeX. Update Documentation/memory-barriers.txt to reflect reality. Cc: Benjamin Herrenschmidt Cc: Arnd Bergmann Cc: David Laight Cc: Alan Stern Cc: Peter Zijlstra Cc: Cc: Cc: Signed-off-by: Will Deacon Signed-off-by: Paul E. McKenney --- Documentation/memory-barriers.txt | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index 1c22b21ae922..a70104e2a087 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -2619,10 +2619,8 @@ functions: intermediary bridges (such as the PCI host bridge) may not fully honour that. - They are guaranteed to be fully ordered with respect to each other. - - They are not guaranteed to be fully ordered with respect to other types of - memory and I/O operation. + They are guaranteed to be fully ordered with respect to each other and + also with respect to other types of memory and I/O operation. (*) readX(), writeX():