From patchwork Wed Dec 19 12:42:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 154260 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4890652ljp; Wed, 19 Dec 2018 04:43:13 -0800 (PST) X-Google-Smtp-Source: AFSGD/VC7I2h9rNPzLY228lMmEq08ZktTkeTLbGzsDDSq2AFsp0yJAxkteQ6be+g/yuWeDr9Tr6C X-Received: by 2002:a17:902:887:: with SMTP id 7mr19987140pll.164.1545223393140; Wed, 19 Dec 2018 04:43:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545223393; cv=none; d=google.com; s=arc-20160816; b=bLNwRjWMu5cNw8GmPJHar9hHjkjLv8q9n6iOpStOcue79yBfArVs6pl61tIXoyP8t6 hvW4d/vxRQGAQ717Rpixxnfj21hQy7yJ+TQbUMw6acpeV9JKiKPmyw6V1WAae9u8Yn97 tw7ggZuuyjCWTdTX+h6LDUwd7gzA3+zeMPzIWpWumdT+BcdZ7190EsmR+CLnTLD6yRtp NFFQLqPHkH//V1qR7shnWjN0Y7ZZB+opzeNFV5nihRSZ7Np+Nj4gATa/jDRxF12sXuhx ogcv2kvQyEyzHbQQBqZoh4UHYUZD8+hGwkkbF5pp58Mx+iIGfKVu6NXKet5Uovjs26sm ytlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=2Znl2d3jLCrX2Ss1Y7tIZm8c5dh8/ypWE14F2Dg39vw=; b=ENdz8Anc852BSmhWkx50mKJ/bO4u7iWjuLtbgyMxbab7x5vQ20pNWVfnGG3n0sJY6h iVsfJJPClv1XTfLzFDYIXq+WCA0zY6ZbMvIM7qvXxVcXm1hJw6MG1/gnNhQGrpJ9UInV BZy4QpfxBM+yYS10raSfvJajDUQ55QsKTtwPNybMAFzMy1A5mn+myQPzSfyUiGIzkCdE WHFWdX9c0ZhWoBrhW6kT3ggdqcUzi51aciDrr6znZJRsRLeaJVsY7up7vb5nWe4cBgT3 j2kXFSTDupEAlp5CjIcRJ9gO7Ka+DnQrKeQ1hl/6mV5F3UySnu+upT5RVZ4KktnQsMJ1 9jcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cN0HBEVN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b7si15858984plk.206.2018.12.19.04.43.12; Wed, 19 Dec 2018 04:43:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cN0HBEVN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729818AbeLSMnL (ORCPT + 31 others); Wed, 19 Dec 2018 07:43:11 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:54848 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729795AbeLSMnI (ORCPT ); Wed, 19 Dec 2018 07:43:08 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id wBJCgmIb098512; Wed, 19 Dec 2018 06:42:48 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1545223369; bh=2Znl2d3jLCrX2Ss1Y7tIZm8c5dh8/ypWE14F2Dg39vw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cN0HBEVN3hmW5fAJ4//i8TIpO2Uq1VPFjduNZEFAw4DShguZl/Ma0+ybS518Kn9KI 3sW9mLXBKH1Jf+dEPs7LFIc1YVnKouteFJdURXnCFDxNfdw/WHqe8X8Thys2ugbFSd 9FblDf/u0bscEcpZ1VtkrrXrl+Q2eTqGTn2RGtLA= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wBJCgmI6034691 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Dec 2018 06:42:48 -0600 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Wed, 19 Dec 2018 06:42:48 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Wed, 19 Dec 2018 06:42:48 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wBJCgNZq003940; Wed, 19 Dec 2018 06:42:45 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi , Gustavo Pimentel , Marc Zyngier CC: Bjorn Helgaas , Jingoo Han , , , , Subject: [PATCH 07/10] PCI: dwc: Add support to use non default msi_irq_chip Date: Wed, 19 Dec 2018 18:12:04 +0530 Message-ID: <20181219124207.13479-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181219124207.13479-1-kishon@ti.com> References: <20181219124207.13479-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Platforms using Designware IP uses dw_pci_msi_bottom_irq_chip for configuring the MSI controller logic within the Designware IP. However certain platforms like Keystone (K2G) which uses Desingware IP has it's own MSI controller logic. For handling such platforms, the irqchip ops uses msi_irq_ack, msi_set_irq, msi_clear_irq callback functions. Add support to use different msi_irq_chip with default as dw_pci_msi_bottom_irq_chip. This is in preparation to get rid off msi_irq_ack, msi_set_irq, msi_clear_irq and other Keystone specific dw_pcie_host_ops. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-host.c | 5 ++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) -- 2.17.1 Acked-by: Gustavo Pimentel diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 0fa9e8fdce66..db21bd11f153 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -245,7 +245,7 @@ static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, for (i = 0; i < nr_irqs; i++) irq_domain_set_info(domain, virq + i, bit + i, - &dw_pci_msi_bottom_irq_chip, + pp->msi_irq_chip, pp, handle_edge_irq, NULL, NULL); @@ -277,6 +277,9 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); + if (!pp->msi_irq_chip) + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; + pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, &dw_pcie_msi_domain_ops, pp); if (!pp->irq_domain) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 0989d880ac46..0873ee4084aa 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -168,6 +168,7 @@ struct pcie_port { struct irq_domain *irq_domain; struct irq_domain *msi_domain; dma_addr_t msi_data; + struct irq_chip *msi_irq_chip; u32 num_vectors; u32 irq_status[MAX_MSI_CTRLS]; raw_spinlock_t lock;