From patchwork Wed Dec 19 12:42:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 154262 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4890778ljp; Wed, 19 Dec 2018 04:43:21 -0800 (PST) X-Google-Smtp-Source: AFSGD/XrEodkr6GN0+uXnY+ST3+neU8TV7egE7OKAhGJDu+7heJ3jm7EX7pO8aK8Fu2wMQvlZut0 X-Received: by 2002:a17:902:365:: with SMTP id 92mr19166991pld.327.1545223401785; Wed, 19 Dec 2018 04:43:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545223401; cv=none; d=google.com; s=arc-20160816; b=sJEUepgYbSfgJMDhA+P01vi0O301XUO7CQv3bKLGxZOrqFkxy7kqGD8Vrrnv2BPmk3 ZLw63hMX8StMqpLBwJDrZC/S+lNN1yS9yKJDei2fXOszYkrwlnQgsUvHEIf15NjTLDZY TqHWNXIZ5//aeYt/fLq8+EspO71eOXn6VY/PAh9XXKxl0nXEY/9Lhz9UTXUlH8o0TF5N s1QkLoReLqu/lp18839SYf9bEQtUZ2+z4o+4uZq2KWyvxgBGphhxM/bd9E7cCBXijlik jL87MuJ2ezJdqRSR9EU7kCrY0W+SJQ/GC9HxtH/2gQBvND/U/vE+gWRh/c15dAqImYLy 355Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=G/xIVDNRUgC00wzBZxvONzU/vnE2y8cZ7NlwEpaC9jQ=; b=FqahvGnFVWq5vOeMsGMf+IGFXhUtQlu8UQmltldkrMhSqccncGCS4dlKmuTy9OsnR8 w7dS662LCTJpperzECSTb+jNd5ZGb9+G9XI6SHn14RA7dMVlkL/8t59TTX+Cd1g5XhT7 ARP5yqfXyV3C8Y6LMfLIkQYWNc2yik3qJTfNZt1SSwVer1dOvB2kuCR4q+9j/lXU8wRB b2NA78gf9K992Om2eoTfzJFsxMuqQf4cvvVgE8F9T2igad9KWvpHvtZtf6LEDo7K4hsr 5jz8L6KoqZjXHiIxQ1OJU5QzudbShETlGJRu4z34EmMPbYB6+s1emq43fBVmzR1MXYYS C+Bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=knZCgQN4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h9si16208598pgb.319.2018.12.19.04.43.21; Wed, 19 Dec 2018 04:43:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=knZCgQN4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729866AbeLSMnT (ORCPT + 31 others); Wed, 19 Dec 2018 07:43:19 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:38694 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729841AbeLSMnQ (ORCPT ); Wed, 19 Dec 2018 07:43:16 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id wBJCgwjO128215; Wed, 19 Dec 2018 06:42:58 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1545223378; bh=G/xIVDNRUgC00wzBZxvONzU/vnE2y8cZ7NlwEpaC9jQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=knZCgQN47O50mIflbtZ4TLDnxTqXySaV+l2A1Sg9CD0PtIw/5zHC/iYclYaTMlqCj gjK6INK/6TEKe0hI/9r6f8OkTBJZdFdE09oPnskvG56DoCxoj9AXHMCOJ7c2pCKOh2 U+JlFrD65xgYPaM3+3ZLhEeu/3HL+7r/MPzwn70g= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wBJCgvV2062483 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Dec 2018 06:42:57 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Wed, 19 Dec 2018 06:42:57 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Wed, 19 Dec 2018 06:42:57 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wBJCgNZt003940; Wed, 19 Dec 2018 06:42:55 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi , Gustavo Pimentel , Marc Zyngier CC: Bjorn Helgaas , Jingoo Han , , , , Subject: [PATCH 10/10] PCI: dwc: Do not write to MSI control registers if the platform doesn't use it Date: Wed, 19 Dec 2018 18:12:07 +0530 Message-ID: <20181219124207.13479-11-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181219124207.13479-1-kishon@ti.com> References: <20181219124207.13479-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Platforms which populate msi_host_init, has it's own MSI controller logic. Writing to MSI control registers on platforms which doesn't use Designware's MSI controller logic might have side effects. To be safe, do not write to MSI control registers if the platform uses it's own MSI controller logic instead of Designware's MSI controller logic. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/dwc/pcie-designware-host.c | 24 ++++++++++--------- 1 file changed, 13 insertions(+), 11 deletions(-) -- 2.17.1 Acked-by: Gustavo Pimentel diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index dbc94f3be3d5..6644a5683b2b 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -647,17 +647,19 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_setup(pci); - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - - /* Initialize IRQ Status array */ - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, ~0); - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, ~0); - pp->irq_status[ctrl] = 0; + if (!pp->ops->msi_host_init) { + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + /* Initialize IRQ Status array */ + for (ctrl = 0; ctrl < num_ctrls; ctrl++) { + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + 4, ~0); + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + 4, ~0); + pp->irq_status[ctrl] = 0; + } } /* Setup RC BARs */