From patchwork Thu Nov 8 18:39:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 150570 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1184173ljp; Thu, 8 Nov 2018 10:41:01 -0800 (PST) X-Google-Smtp-Source: AJdET5eLVpRZUxpOKHzxDffXfg8lOxzWan2jmn1iMSCC3TyjHyyu32bipHrd0JknHVr6X57CWa69 X-Received: by 2002:a17:902:6946:: with SMTP id k6-v6mr893591plt.270.1541702461419; Thu, 08 Nov 2018 10:41:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541702461; cv=none; d=google.com; s=arc-20160816; b=i73lXA6Xw7MrDSo8Ua58rXYtFOwFGMudwYGTIbZPIRnRwotVmwoEfBjUNtRyMCh1eb T60pOhqKjwW5Lec9Eai5qnN+H0Kx9MSsD18PWXA3/vTK+jpa456E4bZn8gI9ALnNAwfN xoFy5bxcgpg3V/GdlvQiYIxV2cGSjuy3XcMaBZcuKD4dlxwrGyVbIH19TZi/iswXGbVZ npdYFWI0y5xVFdALDgaUzAJ2r7IV68Muuoi8y9bP+XEPac8fiuGAJA+kSGR/FEcBqgaR 7EhgL8KRDTwnYN9Ikb0joc21NnAYBnX8PJChIy9ZjtaRGKbOzIUQ+jsUXuiwXoXD1/AD GoIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=xRakDMzmhX1XuRrhweK14oRBxefzP4eSo6lUtz2qVOA=; b=B/xxES/Yj5raYDkKjMdn53OoEKfNmCJWKnnrdfoDS1dP9jIzUzxq00Y0wp8v/wD7Ga UR0FJ6pI4ukf62snWGyKg/AUdVm/DrkU9zdF9/KS41fPlNapEICM9HHf6RNtVY+erfdy ILhh74mc/R5oxqwGzzSd6qODLY7dOk/6r4WgYmwZjZMq0TcBq67+zik4Rbq44YUOKQso 2xvoBBgrbiQxKyn4bYCB0Qy16HuFnZ3nD9qyVxMINO3jgnOizl8k1V78m26Ia+8/jl8L xEBiSrAv64ynH9xCLUuKumypXT7FfjNbg/z/R0dxLP6ycPjtzL1qAZ2TbDp883wuDViH RqsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=Y1vhA6KS; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f21si4187460pgb.371.2018.11.08.10.41.01; Thu, 08 Nov 2018 10:41:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=Y1vhA6KS; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727569AbeKIERq (ORCPT + 32 others); Thu, 8 Nov 2018 23:17:46 -0500 Received: from mail.kernel.org ([198.145.29.99]:59538 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726860AbeKIERq (ORCPT ); Thu, 8 Nov 2018 23:17:46 -0500 Received: from localhost.localdomain (unknown [171.76.98.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id D901E20827; Thu, 8 Nov 2018 18:40:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1541702458; bh=T+p6g0F8jAKv7ODkmKEX/ZT9E4g7uR/098U9KOe2h5o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y1vhA6KS5Y/Qj+xKSfNL3cZsHCkoOJdQj9NtajCszX+k0NGiftmjUHBFecKgo+agg nPVrlyD8y7TAeGnldOEHRicUwBIOlAlQ1KlCddlVqT9Cxoc8LKr2ebn8EUAPR8xeuO sDXdaZ9y8lwqvq59OUuEiestLw4VwBt0hrovcbGE= From: Vinod Koul To: Andy Gross , David Brown Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH v4 01/18] arm64: dts: qcom: qcs404: add base dts files Date: Fri, 9 Nov 2018 00:09:52 +0530 Message-Id: <20181108184009.18430-2-vkoul@kernel.org> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20181108184009.18430-1-vkoul@kernel.org> References: <20181108184009.18430-1-vkoul@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add base dts files for QCS404 chipset along with cpu, timer, gcc and uart2 nodes. Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 175 +++++++++++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs404.dtsi -- 2.14.4 diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi new file mode 100644 index 000000000000..b77d1198ba79 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, Linaro Limited + +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0x0 0 0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc@0 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-qcs404"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + + assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; + assigned-clock-rates = <19200000>; + }; + + blsp1_uart2: serial@78b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b1000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "okay"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + timer@b120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + clock-frequency = <19200000>; + + frame@b121000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = ; + reg = <0x0b123000 0x1000>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = ; + reg = <0x0b124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = ; + reg = <0x0b125000 0x1000>; + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = ; + reg = <0x0b126000 0x1000>; + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = ; + reg = <0xb127000 0x1000>; + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = ; + reg = <0x0b128000 0x1000>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +};