From patchwork Thu Nov 8 17:50:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 150548 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1131626ljp; Thu, 8 Nov 2018 09:52:20 -0800 (PST) X-Google-Smtp-Source: AJdET5dWOlWWpVAyPGQi104bg68RJVHTu9Wufio2xvnvZwyRNyemIKJDXBVq1W8PkEDwGAzkxqwz X-Received: by 2002:a62:704a:: with SMTP id l71-v6mr5453105pfc.68.1541699540263; Thu, 08 Nov 2018 09:52:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541699540; cv=none; d=google.com; s=arc-20160816; b=kfOguJJ2bZKcSo0ZOY2MWIxXdpdrmWAobnXnlqvudrKXQ8aJdeOq4wm5D0JFp8Qo3T CyMImPDfCbpUUAFBAfGR2yJClPFbz8Vp/d+Xux8Kj3TVLMpFZcAeYUhS0S3ZMIDiglJb ex0NIxakcJcX3E9vIoQ/RWWdJE83l3b2JwUDO+7uUxZrWJtWCvcR/NqDh42pAl+djwZe lBRlfrVUJ9wQrnacUvG0p3YGOdk1Pux6LjkkJGi6FZIWFghBgv5ZVvCs4cT/33ZnZqgZ JsrIDEpol2EvZoQ4num/YqBn8+6IePr4Vp3MjYLzMnQY88sriJN1KTzLrjlLfuSO+eTh CnnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=TITlOXNI/8Odlq2ClZ2wtafpCYGkgECSv3VeeyCTjt0=; b=BWloiSM6BSJ5pY3LxoDvqUIhU92ZiY9IWFPAWWR+OHfu4ey88ma+fno6+bXkiMuHgJ GJG41/AI/uUGmcdYvuTBpNnxoryVJvXTQjCVpGjocxiGJJhO7QVOg49CPiGzfAH8A7xd YcrAG1Y0tdCDfweJ+Oyc5x5YV4NCvOjHSA3f+OLZI1qFArKGteqzHh3xIAU/d6wNC2Ix wYNfovzl5ekYCMYkwbPX0NKYmK34PcMXV/MAiKO5LN8vNy1nujQfGwa0B7168LkGbgYb 6uCwAgTWBmaaTGlN1TVKJNPK9+MWyLzxkXPvpJiTSWWB+wjVnZpvrWXDumQuvvpBwmqJ IECg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=WHjY5Lqe; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y68-v6si5080685pfi.61.2018.11.08.09.52.19; Thu, 08 Nov 2018 09:52:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=WHjY5Lqe; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727596AbeKID2w (ORCPT + 32 others); Thu, 8 Nov 2018 22:28:52 -0500 Received: from mail.kernel.org ([198.145.29.99]:40662 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727552AbeKID2w (ORCPT ); Thu, 8 Nov 2018 22:28:52 -0500 Received: from localhost.localdomain (unknown [171.76.98.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id ECEA520827; Thu, 8 Nov 2018 17:52:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1541699536; bh=v5ZNgSy885kUU9ageark3ckSiCBgD/0K9WjoJe1IjOo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WHjY5LqeMN/K4p1nYsPuaDBba/Ahx8NE2e+e8FEuOxvL9a98WPeJAeSebfGn8jO89 QitDSXzZyQFPqtVWUQ3lZKheHU5B+FpaF+1R5w6AbbX8+vU4NyWrxB0qQSunnA/zTy M++yI4z+lwRKzcFbl7EfuNRQwoFY9lbZCXOeR7DU= From: Vinod Koul To: Andy Gross , David Brown Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Andersson , Vinod Koul Subject: [PATCH v3 08/18] arm64: dts: qcom: qcs404: Add sdcc1 node Date: Thu, 8 Nov 2018 23:20:39 +0530 Message-Id: <20181108175049.7090-9-vkoul@kernel.org> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20181108175049.7090-1-vkoul@kernel.org> References: <20181108175049.7090-1-vkoul@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Bjorn Andersson Add the sdcc1 node and enable it for the QCS404-EVB. Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 64 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/qcs404.dtsi | 17 +++++++++ 2 files changed, 81 insertions(+) -- 2.14.4 diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index fc83e935aaa1..4d2ada8dec5d 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -109,3 +109,67 @@ }; }; }; + +&sdcc1 { + status = "ok"; + + mmc-ddr-1_8v; + bus-width = <8>; + non-removable; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&tlmm { + sdc1_on: sdc1-on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + dreive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1-off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + dreive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 3b6e659e3d1f..e83b7c233099 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -181,6 +181,23 @@ reg = <0x01905000 0x20000>; }; + sdcc1: sdcc@7804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x07804000 0x1000>, <0x7805000 0x1000>; + reg-names = "hc_mem", "cmdq_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + + status = "disabled"; + }; + blsp1_uart2: serial@78b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078b1000 0x200>;