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[209.132.180.67]) by mx.google.com with ESMTP id w19-v6si10155009pgf.197.2018.10.17.00.43.31; Wed, 17 Oct 2018 00:43:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RnhcslOh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727688AbeJQPh3 (ORCPT + 32 others); Wed, 17 Oct 2018 11:37:29 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:60654 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727257AbeJQPh2 (ORCPT ); Wed, 17 Oct 2018 11:37:28 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9H7ghFY053901; Wed, 17 Oct 2018 02:42:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1539762163; bh=7J6+SCgM8p61/w90SEo09MilVPmCdhutv9TiE9uHRPU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RnhcslOhHQZXwSn6baYeJJu7tIaWD7mdPzbOtc4dvI/0L/lfC3lvEkNBCx9VhKHWs R24M92MjkBsdWgH5P0petDkrJ8HDeXW0lUvfYtrF3PVqP3ts5oGRiZ+IEpu+tNdXu+ wuNFSb7V4s64NfNxkM6tG3Yzhc8gSNLifqp/EyLQ= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9H7ghLp009845; Wed, 17 Oct 2018 02:42:43 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 17 Oct 2018 02:42:42 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 17 Oct 2018 02:42:42 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9H7fgSc009413; Wed, 17 Oct 2018 02:42:40 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Murali Karicheri , Jingoo Han , Gustavo Pimentel CC: Rob Herring , , , , , Kishon Vijay Abraham I Subject: [PATCH v2 17/21] PCI: keystone: Cleanup ks_pcie_link_up() Date: Wed, 17 Oct 2018 13:11:10 +0530 Message-ID: <20181017074114.28239-18-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181017074114.28239-1-kishon@ti.com> References: <20181017074114.28239-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ks_pcie_link_up() uses registers from the designware core to get the status of the link. Move the register defines to pcie-designware.h and cleanup ks_pcie_link_up(). Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 11 +++-------- drivers/pci/controller/dwc/pcie-designware.h | 4 ++++ 2 files changed, 7 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 2decbaec81a3..e181e6277323 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -38,8 +38,6 @@ /* Application register defines */ #define LTSSM_EN_VAL BIT(0) -#define LTSSM_STATE_MASK 0x1f -#define LTSSM_STATE_L0 0x11 #define DBI_CS2 BIT(5) #define OB_XLAT_EN_VAL BIT(1) @@ -87,11 +85,7 @@ #define ERR_IRQ_ENABLE_SET 0x1c8 #define ERR_IRQ_ENABLE_CLR 0x1cc -/* Config space registers */ -#define DEBUG0 0x728 - #define MAX_MSI_HOST_IRQS 8 - /* PCIE controller device IDs */ #define PCIE_RC_K2HK 0xb008 #define PCIE_RC_K2E 0xb009 @@ -442,8 +436,9 @@ static int ks_pcie_link_up(struct dw_pcie *pci) { u32 val; - val = dw_pcie_readl_dbi(pci, DEBUG0); - return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0; + val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); + val &= PORT_LOGIC_LTSSM_STATE_MASK; + return (val == PORT_LOGIC_LTSSM_STATE_L0); } static void ks_pcie_initiate_link_train(struct keystone_pcie *ks_pcie) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 9f1a5e399b70..0989d880ac46 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -36,6 +36,10 @@ #define PORT_LINK_MODE_4_LANES (0x7 << 16) #define PORT_LINK_MODE_8_LANES (0xf << 16) +#define PCIE_PORT_DEBUG0 0x728 +#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f +#define PORT_LOGIC_LTSSM_STATE_L0 0x11 + #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)