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[209.132.180.67]) by mx.google.com with ESMTP id p12-v6si4165819pfj.244.2018.09.27.23.48.35; Thu, 27 Sep 2018 23:48:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MaprZxME; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729119AbeI1NKs (ORCPT + 32 others); Fri, 28 Sep 2018 09:10:48 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:43319 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726473AbeI1NKr (ORCPT ); Fri, 28 Sep 2018 09:10:47 -0400 Received: by mail-pg1-f196.google.com with SMTP id q19-v6so3715649pgn.10 for ; Thu, 27 Sep 2018 23:48:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4VJX5OtbVz8vzfF/CMl4UANq631qfAiD/HWUtm1wpWw=; b=MaprZxMEOptN6Y1PB4m8DaHjLUv1xwZglze7vHiCUBjtXFko9ADVOqvNtzuND72J6M yyckY2B3mKQKPzbxBQVTmVIbaPPw678THitZlBL9FdvrHCAq7Fm7knKejpDVshXvDsOC 9zlI5QDH9W7qxx4BpPrbX1kMrApuilWGjHMhk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4VJX5OtbVz8vzfF/CMl4UANq631qfAiD/HWUtm1wpWw=; b=kIv3KZ82KRG41jVBXxVMo3NVl3OnT2D9aj5uVOOx++3typGbP4g4n3OhWviS5gN+YY oDnhA8LBZkLdRUhktNKl5OVEWVq9Ya35g4PjTV3XDpPqEbBbAGzi+w6iIJYB7LtzfdqV hDe3VhEq4d3WmkhBGy+uJ0TfMd8ptbaLAa1I/mW3Pn0rTYUvbRDtWWf85Q0SAhwXveTb co3OyiLHmmLM9C/K0g6IBzBZMq1lLpEnzz9dX3T/t45Qsc5Z821oc7dldxfZ6NcvEdtX omkW3PdxJPOMZPxmujnEZOzNvFQ+oHtBFuS+hb2yO1xYeKvxBMqdJFpmb5HFAOvKUFV1 DRlQ== X-Gm-Message-State: ABuFfoi+JSgAAM2nJWVG2Vz6hAnIxuF/KJ4pUtV8Fkz/lAaFat0qKUTF g8EaNUmuPv5CvkEyaBXpIBQv8w== X-Received: by 2002:a62:384c:: with SMTP id f73-v6mr15351621pfa.242.1538117312657; Thu, 27 Sep 2018 23:48:32 -0700 (PDT) Received: from linaro.org ([121.95.100.191]) by smtp.googlemail.com with ESMTPSA id c85-v6sm5903582pfb.147.2018.09.27.23.48.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 27 Sep 2018 23:48:31 -0700 (PDT) From: AKASHI Takahiro To: catalin.marinas@arm.com, will.deacon@arm.com, dhowells@redhat.com, vgoyal@redhat.com, herbert@gondor.apana.org.au, davem@davemloft.net, dyoung@redhat.com, bhe@redhat.com, arnd@arndb.de, schwidefsky@de.ibm.com, heiko.carstens@de.ibm.com Cc: prudo@linux.ibm.com, ard.biesheuvel@linaro.org, james.morse@arm.com, bhsharma@redhat.com, kexec@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, AKASHI Takahiro Subject: [PATCH v15 08/16] arm64: cpufeature: add MMFR0 helper functions Date: Fri, 28 Sep 2018 15:48:33 +0900 Message-Id: <20180928064841.14117-9-takahiro.akashi@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180928064841.14117-1-takahiro.akashi@linaro.org> References: <20180928064841.14117-1-takahiro.akashi@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Those helper functions for MMFR0 register will be used later by kexec_file loader. Signed-off-by: AKASHI Takahiro Cc: Catalin Marinas Cc: Will Deacon Reviewed-by: James Morse --- arch/arm64/include/asm/cpufeature.h | 48 +++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 2.19.0 diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 1717ba1db35d..cd90b5252d6d 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -486,11 +486,59 @@ static inline bool system_supports_32bit_el0(void) return cpus_have_const_cap(ARM64_HAS_32BIT_EL0); } +static inline bool system_supports_4kb_granule(void) +{ + u64 mmfr0; + u32 val; + + mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); + val = cpuid_feature_extract_unsigned_field(mmfr0, + ID_AA64MMFR0_TGRAN4_SHIFT); + + return val == ID_AA64MMFR0_TGRAN4_SUPPORTED; +} + +static inline bool system_supports_64kb_granule(void) +{ + u64 mmfr0; + u32 val; + + mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); + val = cpuid_feature_extract_unsigned_field(mmfr0, + ID_AA64MMFR0_TGRAN64_SHIFT); + + return val == ID_AA64MMFR0_TGRAN64_SUPPORTED; +} + +static inline bool system_supports_16kb_granule(void) +{ + u64 mmfr0; + u32 val; + + mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); + val = cpuid_feature_extract_unsigned_field(mmfr0, + ID_AA64MMFR0_TGRAN16_SHIFT); + + return val == ID_AA64MMFR0_TGRAN16_SUPPORTED; +} + static inline bool system_supports_mixed_endian_el0(void) { return id_aa64mmfr0_mixed_endian_el0(read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1)); } +static inline bool system_supports_mixed_endian(void) +{ + u64 mmfr0; + u32 val; + + mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); + val = cpuid_feature_extract_unsigned_field(mmfr0, + ID_AA64MMFR0_BIGENDEL_SHIFT); + + return val == 0x1; +} + static inline bool system_supports_fpsimd(void) { return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD);