From patchwork Fri Sep 21 15:08:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 147284 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp935569ljw; Fri, 21 Sep 2018 08:10:02 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbUoa6MW5UAsGK0iE8BgrRHU8dMxolpCZeDSXOfFqJ6b6Sc97h5xkQZWRkoyMYUyZ5nqVIR X-Received: by 2002:a17:902:2e83:: with SMTP id r3-v6mr44931925plb.80.1537542602795; Fri, 21 Sep 2018 08:10:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537542602; cv=none; d=google.com; s=arc-20160816; b=uAs3UALw1YxWfvDJY9Wm9Kp2AwzqicvVgl60fKqqccQ8Z3nw+pGg9OB4I6nWMKiolR ujD9eMYUJd5XepRVxg4U8d0KrJyyDNu3MSqL9c/KPQAjVtGS0wmGRJK9+L26yun71t/A hX5gkIVIBgiImIqrGpz9vZRsciF7jHxLN20oEMOmkyVcF3q3eQUqGqREc0QBs6C5KInz 4y6Y8Q9TCt9GoAENEg39fHDIyWY4fYljNX8e9d57c7yLxwC3ItQpM3PB8rEWouRlympv W5UZUcCgOqO2axSA+erjGykwUV9+MGF0r6fzeQuzAc4iPI1NLrSJ4dpRetALmXjrID8J g+ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=AbAvyXh8sa0d8SnkxFkb3sayf7139K9Xc2fTBsXpago=; b=sKjJK/QeYzIiuneSzyH5Zyy+4Wa2goSF2PiPLsF/XK1mTBBLIu2bMFaAgmLXztXLXf topl/uLNi82Zdc7m9lAL4zRzFJdbUm6LwbEJ2sN4r81jAhrs2GSC9W+Nj9fEP2ehtGb+ J7jFZO+IQWi5pnuVL0RN6XMbwptORXiESJE5QX8tefRvQsZ0RXYt0ktezst2JZkON/lE Y/4HzDMr+vOqTW7U90vaE8rZN61lBA1nloGMvJv47vsJTaasAIYTgw1F7rZWuq++SsLq +YQwLec7QvGL/mj2xuX3uaEcoSqn/VI+ND2Xih7LgMjncrVUokrg3R0yf8ZYTKOV0PAo INqQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n37-v6si27084579pgb.43.2018.09.21.08.10.02; Fri, 21 Sep 2018 08:10:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390713AbeIUU7S (ORCPT + 32 others); Fri, 21 Sep 2018 16:59:18 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:39218 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2390248AbeIUU7N (ORCPT ); Fri, 21 Sep 2018 16:59:13 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id E9161D1817A52; Fri, 21 Sep 2018 23:09:43 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.399.0; Fri, 21 Sep 2018 23:09:36 +0800 From: Shameer Kolothum To: , CC: , , , , , , , , , , , Subject: [PATCH v3 3/3] perf/smmuv3: Add MSI irq support Date: Fri, 21 Sep 2018 16:08:03 +0100 Message-ID: <20180921150803.25444-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20180921150803.25444-1-shameerali.kolothum.thodi@huawei.com> References: <20180921150803.25444-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds support for MSI-based counter overflow interrupt. Signed-off-by: Shameer Kolothum --- drivers/perf/arm_smmuv3_pmu.c | 58 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) -- 2.7.4 diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c index 2fa6c96..84f7907 100644 --- a/drivers/perf/arm_smmuv3_pmu.c +++ b/drivers/perf/arm_smmuv3_pmu.c @@ -57,6 +57,7 @@ #define SMMU_PMCG_OVSSET0 0xCC0 #define SMMU_PMCG_CFGR 0xE00 #define SMMU_PMCG_CFGR_RELOC_CTRS BIT(20) +#define SMMU_PMCG_CFGR_MSI BIT(21) #define SMMU_PMCG_CFGR_SIZE_MASK GENMASK(13, 8) #define SMMU_PMCG_CFGR_NCTR_MASK GENMASK(5, 0) #define SMMU_PMCG_CR 0xE04 @@ -66,6 +67,12 @@ #define SMMU_PMCG_IRQ_CTRL 0xE50 #define SMMU_PMCG_IRQ_CTRL_IRQEN BIT(0) #define SMMU_PMCG_IRQ_CFG0 0xE58 +#define SMMU_PMCG_IRQ_CFG1 0xE60 +#define SMMU_PMCG_IRQ_CFG2 0xE64 + +/* MSI config fields */ +#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2) +#define MSI_CFG2_MEMATTR_DEVICE_nGnRE 0x1 #define SMMU_DEFAULT_FILTER_SPAN 1 #define SMMU_DEFAULT_FILTER_STREAM_ID GENMASK(31, 0) @@ -548,11 +555,62 @@ static irqreturn_t smmu_pmu_handle_irq(int irq_num, void *data) return IRQ_HANDLED; } +static void smmu_pmu_free_msis(void *data) +{ + struct device *dev = data; + + platform_msi_domain_free_irqs(dev); +} + +static void smmu_pmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + phys_addr_t doorbell; + struct device *dev = msi_desc_to_dev(desc); + struct smmu_pmu *pmu = dev_get_drvdata(dev); + + doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo; + doorbell &= MSI_CFG0_ADDR_MASK; + + writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); + writel_relaxed(msg->data, pmu->reg_base + SMMU_PMCG_IRQ_CFG1); + writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE, + pmu->reg_base + SMMU_PMCG_IRQ_CFG2); +} + +static void smmu_pmu_setup_msi(struct smmu_pmu *pmu) +{ + struct msi_desc *desc; + struct device *dev = pmu->dev; + int ret; + + /* Clear MSI address reg */ + writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); + + /* MSI supported or not */ + if (!(readl(pmu->reg_base + SMMU_PMCG_CFGR) & SMMU_PMCG_CFGR_MSI)) + return; + + ret = platform_msi_domain_alloc_irqs(dev, 1, smmu_pmu_write_msi_msg); + if (ret) { + dev_warn(dev, "failed to allocate MSIs\n"); + return; + } + + desc = first_msi_entry(dev); + if (desc) + pmu->irq = desc->irq; + + /* Add callback to free MSIs on teardown */ + devm_add_action(dev, smmu_pmu_free_msis, dev); +} + static int smmu_pmu_setup_irq(struct smmu_pmu *pmu) { unsigned long flags = IRQF_NOBALANCING | IRQF_SHARED | IRQF_NO_THREAD; int irq, ret = -ENXIO; + smmu_pmu_setup_msi(pmu); + irq = pmu->irq; if (irq) ret = devm_request_irq(pmu->dev, irq, smmu_pmu_handle_irq,