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[209.132.180.67]) by mx.google.com with ESMTP id f1-v6si29944582plm.437.2018.09.21.03.24.32; Fri, 21 Sep 2018 03:24:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=SrRhTJTz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390093AbeIUQMn (ORCPT + 32 others); Fri, 21 Sep 2018 12:12:43 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35132 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389022AbeIUQMm (ORCPT ); Fri, 21 Sep 2018 12:12:42 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAO7nP030566; Fri, 21 Sep 2018 05:24:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525447; bh=WfasnAWlcLsVQTlj7zbQefyfmRm0OJVS8gwd8Y4RkZE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SrRhTJTz9S1YGp1cSnqA9NSf+jCq0J0fPTAw2g58MEk803aF/ww1fL9j8nkVah+er C1Yx6OpQL/p4jhS1qWtd4+dubliONkeS2nKYIRPYbzeljqV9VX1/QiVhp2FpsbGk/D eM0E8OeDURs5LzqGK1UdgyblacV8X/0ah+KRlb8Y= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAO7K6019745; Fri, 21 Sep 2018 05:24:07 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:24:07 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:24:07 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtR032280; Fri, 21 Sep 2018 05:24:03 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 23/40] PCI: keystone: Cleanup macros defined in pci-keystone.c Date: Fri, 21 Sep 2018 15:51:38 +0530 Message-ID: <20180921102155.22839-24-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Cleanup macros defined in pci-keystone.c by removing unused macros, grouping the macros and aligning it properly. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 41 +++++++++-------------- 1 file changed, 16 insertions(+), 25 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index b1dfaea29530..75d007148804 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -28,21 +28,14 @@ #include "pcie-designware.h" -#define DRIVER_NAME "keystone-pcie" - #define PCIE_VENDORID_MASK 0xffff #define PCIE_DEVICEID_SHIFT 16 -/* DEV_STAT_CTRL */ -#define PCIE_CAP_BASE 0x70 - -/* Application register defines */ -#define LTSSM_EN_VAL BIT(0) -#define DBI_CS2 BIT(5) -#define OB_XLAT_EN_VAL BIT(1) - /* Application registers */ #define CMD_STATUS 0x004 +#define LTSSM_EN_VAL BIT(0) +#define OB_XLAT_EN_VAL BIT(1) +#define DBI_CS2 BIT(5) #define CFG_SETUP 0x008 #define CFG_BUS(x) (((x) & 0xff) << 16) @@ -65,18 +58,16 @@ #define IRQ_ENABLE_SET(n) (0x188 + ((n) << 4)) #define INTx_EN BIT(0) -/* Error IRQ bits */ -#define ERR_AER BIT(5) /* ECRC error */ -#define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ -#define ERR_CORR BIT(3) /* Correctable error */ -#define ERR_NONFATAL BIT(2) /* Non-fatal error */ -#define ERR_FATAL BIT(1) /* Fatal error */ -#define ERR_SYS BIT(0) /* System (fatal, non-fatal, or correctable) */ -#define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ - ERR_NONFATAL | ERR_FATAL | ERR_SYS) #define ERR_IRQ_STATUS 0x1c4 #define ERR_IRQ_ENABLE_SET 0x1c8 -#define ERR_IRQ_ENABLE_CLR 0x1cc +#define ERR_AER BIT(5) /* ECRC error */ +#define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ +#define ERR_CORR BIT(3) /* Correctable error */ +#define ERR_NONFATAL BIT(2) /* Non-fatal error */ +#define ERR_FATAL BIT(1) /* Fatal error */ +#define ERR_SYS BIT(0) /* System error */ +#define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ + ERR_NONFATAL | ERR_FATAL | ERR_SYS) #define OB_OFFSET_INDEX(n) (0x200 + (8 * (n))) #define OB_ENABLEN BIT(0) @@ -84,12 +75,12 @@ #define OB_OFFSET_HI(n) (0x204 + (8 * (n))) /* PCIE controller device IDs */ -#define PCIE_RC_K2HK 0xb008 -#define PCIE_RC_K2E 0xb009 -#define PCIE_RC_K2L 0xb00a -#define PCIE_RC_K2G 0xb00b +#define PCIE_RC_K2HK 0xb008 +#define PCIE_RC_K2E 0xb009 +#define PCIE_RC_K2L 0xb00a +#define PCIE_RC_K2G 0xb00b -#define to_keystone_pcie(x) dev_get_drvdata((x)->dev) +#define to_keystone_pcie(x) dev_get_drvdata((x)->dev) static int ks_pcie_start_link(struct dw_pcie *pci); static void ks_pcie_stop_link(struct dw_pcie *pci);