From patchwork Sun Aug 12 09:47:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Salil Mehta X-Patchwork-Id: 143986 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1892587ljj; Sun, 12 Aug 2018 02:49:01 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxEU0L1AMoQukIsoXqsDqA8kSWBMLucGp/IaNQK89xMeE4TuppWBlxqGLwn38booFll04t/ X-Received: by 2002:a63:7558:: with SMTP id f24-v6mr13189829pgn.314.1534067341261; Sun, 12 Aug 2018 02:49:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534067341; cv=none; d=google.com; s=arc-20160816; b=ZFQwzAl+FV8Jl22Urkgr2rxm/Ttv8y6NBNEdMesS8m7Clr+5wQReHlkJAdi7MIz7n6 AGdFAAyzjFlVYFHIPlFaVGlRXUKnQD4PYKiOppmUGnA0NgzWY9uK3x9wgFGzqApZK5qI uGZbgOY6Ck5hSlhgIQyqRHu2iWjoxxlNS4cTNGgfutw8fjA/JGQB1jnWFGGRM9cf/iM/ ZHxQ6fibbpYUlcGYQIJV6IaBp78f4vN/1sw5EO+juD/C5R+rwIQ88pTUh3XEtKe+6bRL o04pRi9yBYDmeHHD68cAiwh+2y74leBwFIG26ChVRs/UPq9agLwcGz8mz7ivfAha0U7m HXJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=jIYHyC75yVa01JoUoxYRwWBe8ty7UsbLv+mbqS+8eKY=; b=vihNH3mWtOBV9r5EU3ipfYN94ONZsQqziZccD0vwLIhtQ+o61kdmHFntyIAcTETG/9 tek49+ug+Ze0Y+HBTzmxabNM1QZVAms6Mev25FS+b2HhZyAU6pI5aLKDFcuBzxHk1J8l z3I7tyo4OJzqIHFj8fvmTWu80xys8iZ3tyDgQg37NSL2cRvsfIPMe+1LackVvTAZVwP/ HWuKZvrxzSqUZPQEFTb1AOW5DaLtLJLekZ04WSg2rO3RW9lh/uSAV2zD15fJYhsd6X3h vqU9/QZ8aRHX1eIJh9WpYNYXF/xKv2KmZRJEAoMik2ClLrzLxA7kPfBrDgwGoeeoa67U jSgA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t89-v6si15784334pfe.59.2018.08.12.02.49.01; Sun, 12 Aug 2018 02:49:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728149AbeHLM0Z (ORCPT + 31 others); Sun, 12 Aug 2018 08:26:25 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:36887 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727826AbeHLM0Z (ORCPT ); Sun, 12 Aug 2018 08:26:25 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id CFC9CA68CA49D; Sun, 12 Aug 2018 17:48:54 +0800 (CST) Received: from S00293818-DELL1.china.huawei.com (10.47.93.119) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.399.0; Sun, 12 Aug 2018 17:48:46 +0800 From: Salil Mehta To: CC: , , , , , , , Yunsheng Lin Subject: [PATCH net-next 8/9] net: hns3: Set tx ring' tc info when netdev is up Date: Sun, 12 Aug 2018 10:47:37 +0100 Message-ID: <20180812094738.14852-9-salil.mehta@huawei.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20180812094738.14852-1-salil.mehta@huawei.com> References: <20180812094738.14852-1-salil.mehta@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.93.119] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yunsheng Lin The HNS3_RING_TX_RING_TC_REG register is used to map tx ring to specific tc, the tx queue to tc mapping is needed by the hardware to do the correct tx schedule. Signed-off-by: Yunsheng Lin Signed-off-by: Peng Li Signed-off-by: Salil Mehta --- drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 24 ++++++++++++++++++++++++ drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 1 + 2 files changed, 25 insertions(+) -- 2.11.0 diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c index b7b9ee3f4d20..b28c7e142308 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c @@ -2974,6 +2974,28 @@ static void hns3_init_ring_hw(struct hns3_enet_ring *ring) } } +static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) +{ + struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; + int i; + + for (i = 0; i < HNAE3_MAX_TC; i++) { + struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; + int j; + + if (!tc_info->enable) + continue; + + for (j = 0; j < tc_info->tqp_count; j++) { + struct hnae3_queue *q; + + q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp; + hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, + tc_info->tc); + } + } +} + int hns3_init_all_ring(struct hns3_nic_priv *priv) { struct hnae3_handle *h = priv->ae_handle; @@ -3385,6 +3407,8 @@ int hns3_nic_reset_all_ring(struct hnae3_handle *h) rx_ring->next_to_use = 0; } + hns3_init_tx_ring_tc(priv); + return 0; } diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h index 0f071a0f4ff9..a02a96aee2a2 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h @@ -37,6 +37,7 @@ enum hns3_nic_state { #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048 +#define HNS3_RING_TX_RING_TC_REG 0x00050 #define HNS3_RING_TX_RING_TAIL_REG 0x00058 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060