From patchwork Mon Jul 16 15:36:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Salil Mehta X-Patchwork-Id: 142031 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2568351ljj; Mon, 16 Jul 2018 08:37:28 -0700 (PDT) X-Google-Smtp-Source: AAOMgpd4WUL/Up7NxGf/o20L4vRqO4FKZUZcdSes/Y4vNHhqh91L5zJP4uN0tp/L4u4TzFCCogio X-Received: by 2002:a63:6501:: with SMTP id z1-v6mr16216021pgb.419.1531755447877; Mon, 16 Jul 2018 08:37:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531755447; cv=none; d=google.com; s=arc-20160816; b=zgQoCNEcDuZbR2Xt8jLQkzYg3GPmjgJ2dB5ofrfjGkT839k07d7sx2XQ6K+jktZD2B tRhb7//xrCAwu+MmTqdhbCRg/yK+FawC18eVP/XtQZaPPiQW3crpZDm3AtforAGQ+Wr6 47sdNHtgpkvW+zQowmEPWghhRAPZ2D3TT5Hs6IPEeh8wgirM1TBc7IYtIQ88c2CWNN6e gozk8wbaVtV3Ch9Hag5a+G0lD1LB6yAkaMqjKtQnTpe/K0lHmK0ee/ER5M2s/zifsk/Z PXA+DJtrDQuKZVvBDd6v+Zzrh/cebACz+/7+F8KhZefijo/ux+ca5CysqUtT1SYlf/s5 KCrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=c7IVz6eDE3XBUlt/kcLj14dlrJikPq3bY2CtlDJe5OY=; b=EdcOcp6CD1ow1Mudp7fgIX/Gap6BUBcK0Mf8yC/oQa6lvHlkl5xFaUu06jUCZ3+/9l ztMHZK1MxY20NTS/3kM3LXqhwPlGiMjbIvzPwFE9vn4MQMTgF+bGT1mmmJ1Y/fuOtuk/ 2KlEJoroDUPtQlwd5LipSziEuZ+JZ1mL5cKxv3ASHR+9HorlGXtZ+mvb4XpecrTqN6Y1 r0h7K3wu168f17RZYdQQOmwKgsd230jApCCg/mQSAEzpqPQMxjyenTqcaXgVPGsEZkAA yG+6weRWLXuktiEsTpYfzVPhnLrjeHf+3uaJHPV3CH27Nsue6TnegPYb5lZ8GeldWcOH IWZw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g33-v6si31615058plb.297.2018.07.16.08.37.27; Mon, 16 Jul 2018 08:37:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730043AbeGPQFV (ORCPT + 31 others); Mon, 16 Jul 2018 12:05:21 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:46269 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727957AbeGPQFV (ORCPT ); Mon, 16 Jul 2018 12:05:21 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id BE95CA4782E65; Mon, 16 Jul 2018 23:37:18 +0800 (CST) Received: from S00293818-DELL1.huawei.com (10.202.226.54) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.382.0; Mon, 16 Jul 2018 23:37:12 +0800 From: Salil Mehta To: CC: , , , , , , , Huazhong Tan Subject: [PATCH net-next 4/9] net: hns3: Correct reset event status register Date: Mon, 16 Jul 2018 16:36:22 +0100 Message-ID: <20180716153627.476-5-salil.mehta@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716153627.476-1-salil.mehta@huawei.com> References: <20180716153627.476-1-salil.mehta@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.226.54] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Huazhong Tan According to hardware's description, driver should get reset event from VECTOR0_PF_OTHER_INT_ST(0x20800) instead of VECTOR0_PF_OTHER_INT_SRC(0x20700). Signed-off-by: Huazhong Tan Signed-off-by: Peng Li Signed-off-by: Salil Mehta --- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 2 +- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index a1886a3..266c686 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -2495,7 +2495,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) u32 cmdq_src_reg; /* fetch the events from their corresponding regs */ - rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG); + rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); /* Assumption: If by any chance reset and mailbox events are reported diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index 20abe82..a5abf8e 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -89,6 +89,7 @@ /* Reset related Registers */ #define HCLGE_MISC_RESET_STS_REG 0x20700 +#define HCLGE_MISC_VECTOR_INT_STS 0x20800 #define HCLGE_GLOBAL_RESET_REG 0x20A00 #define HCLGE_GLOBAL_RESET_BIT 0x0 #define HCLGE_CORE_RESET_BIT 0x1