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[209.132.180.67]) by mx.google.com with ESMTP id y2-v6si18325308plp.459.2018.07.11.00.42.24; Wed, 11 Jul 2018 00:42:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z230q3lp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727215AbeGKHpR (ORCPT + 22 others); Wed, 11 Jul 2018 03:45:17 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:40889 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726410AbeGKHpR (ORCPT ); Wed, 11 Jul 2018 03:45:17 -0400 Received: by mail-pl0-f66.google.com with SMTP id t6-v6so8805230plo.7 for ; Wed, 11 Jul 2018 00:42:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uswfCd93e0qJR+3NeyRPsd43EHwi1pdW3kTaED3pE8E=; b=Z230q3lpLDRUO6KPcurb/pBZplwXRi3kDbCO5IKatDsR5+61CIDNH/2fUz7wt8TVkS DXiuYnbeD49VFg/sRwO6VMmmPZMPxYNLDgMecIoUkF2KcYi8Xh7Mp1RdCBLFOhxr6ti9 bkzYt9naojosaLZ+tUhDg3OLCJWgRdMRVVsNg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uswfCd93e0qJR+3NeyRPsd43EHwi1pdW3kTaED3pE8E=; b=C1xMK837Kr8iCad3OeiSjF/GyBCQ8i4NmUVsSqHVgjoBGog9a1NDwSf25SSeF/pI3k mIh+wXq3KvC35onZYAJz6REfzRuQSxgQ69OAXESetsPRgqGxwaSq1E6t7Um2wxwFI4bm 1oCVfvUwOfkMtA4pvNIEJwP/XsyftelwG5OMoIOpH7OS8e81Uj3Y7v7deR9If2oJtLiT 5SxpGhQyBTUodQRJA9mKIikszRGLGkTCp5kO3r1jWFZZtk5m+81bM5ddqZF/dQM32Cv0 BBKj7yFUuQhXYc+uKfBTNWeMiVuwFACuHt9dK50hwX15DJpQDCrmR23BhldBUuUcnt5J 5C/g== X-Gm-Message-State: APt69E1CvlefoIxXEAwx5ZL5n1mmHWieM7jytO46yWZop0TRiHsUkgf9 zOgzHSUd+1yJKwg2XKz9N+kmcQ== X-Received: by 2002:a17:902:a60b:: with SMTP id u11-v6mr27620867plq.158.1531294941053; Wed, 11 Jul 2018 00:42:21 -0700 (PDT) Received: from linaro.org ([121.95.100.191]) by smtp.googlemail.com with ESMTPSA id q28-v6sm36911949pfg.144.2018.07.11.00.42.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Jul 2018 00:42:20 -0700 (PDT) From: AKASHI Takahiro To: catalin.marinas@arm.com, will.deacon@arm.com, dhowells@redhat.com, vgoyal@redhat.com, herbert@gondor.apana.org.au, davem@davemloft.net, dyoung@redhat.com, bhe@redhat.com, arnd@arndb.de Cc: ard.biesheuvel@linaro.org, james.morse@arm.com, bhsharma@redhat.com, kexec@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, AKASHI Takahiro Subject: [PATCH v11 07/15] arm64: cpufeature: add MMFR0 helper functions Date: Wed, 11 Jul 2018 16:41:55 +0900 Message-Id: <20180711074203.3019-8-takahiro.akashi@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180711074203.3019-1-takahiro.akashi@linaro.org> References: <20180711074203.3019-1-takahiro.akashi@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Those helper functions for MMFR0 register will be used later by kexec_file loader. Signed-off-by: AKASHI Takahiro Cc: Catalin Marinas Cc: Will Deacon Reviewed-by: James Morse --- arch/arm64/include/asm/cpufeature.h | 48 +++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 2.17.0 diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 1717ba1db35d..cd90b5252d6d 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -486,11 +486,59 @@ static inline bool system_supports_32bit_el0(void) return cpus_have_const_cap(ARM64_HAS_32BIT_EL0); } +static inline bool system_supports_4kb_granule(void) +{ + u64 mmfr0; + u32 val; + + mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); + val = cpuid_feature_extract_unsigned_field(mmfr0, + ID_AA64MMFR0_TGRAN4_SHIFT); + + return val == ID_AA64MMFR0_TGRAN4_SUPPORTED; +} + +static inline bool system_supports_64kb_granule(void) +{ + u64 mmfr0; + u32 val; + + mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); + val = cpuid_feature_extract_unsigned_field(mmfr0, + ID_AA64MMFR0_TGRAN64_SHIFT); + + return val == ID_AA64MMFR0_TGRAN64_SUPPORTED; +} + +static inline bool system_supports_16kb_granule(void) +{ + u64 mmfr0; + u32 val; + + mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); + val = cpuid_feature_extract_unsigned_field(mmfr0, + ID_AA64MMFR0_TGRAN16_SHIFT); + + return val == ID_AA64MMFR0_TGRAN16_SUPPORTED; +} + static inline bool system_supports_mixed_endian_el0(void) { return id_aa64mmfr0_mixed_endian_el0(read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1)); } +static inline bool system_supports_mixed_endian(void) +{ + u64 mmfr0; + u32 val; + + mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); + val = cpuid_feature_extract_unsigned_field(mmfr0, + ID_AA64MMFR0_BIGENDEL_SHIFT); + + return val == 0x1; +} + static inline bool system_supports_fpsimd(void) { return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD);