From patchwork Fri Jul 6 10:27:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Salil Mehta X-Patchwork-Id: 141292 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2947361ljj; Fri, 6 Jul 2018 03:31:42 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdR88rS2ATMUhWvqxxgXGUlbBDsxkWU4DYNmfKoDa9rNLG+nfv5Q7O/zaV9McjV3g+XOpPu X-Received: by 2002:a63:d518:: with SMTP id c24-v6mr2864065pgg.357.1530873102315; Fri, 06 Jul 2018 03:31:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530873102; cv=none; d=google.com; s=arc-20160816; b=SaeKNymc12lPlZNiE7nIqKW5NPoZmlfhQ08xwUEHtKD2xomweC1xy1xi0g9ma3wCEV XDRMnxCiDvP7v+PvAWGoonQCq/LBBG6Ron8Cfw3lPbwQ/DVeqimggClsnylu56nYJ+Vw aWgDkjQWnQoiIMcj2l0N2q9oON//06CDXBdwdBsqKz56Vm59JJ/CxU25PckPfOC1P27H Dhm4hVfmxv5Ht+Wzx496LRYkMiUv0xc1tAa/HFGAWfDjrXaTUfXUH4Zbcykp1TruhWMy FqwIbJKa7lofx4uA5x2NVzr/exl8XNtD1LA9os8jYzhCoNauPi5QqywkChzxXBl04Epn eSJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=uvlPd2uKNE5dZdzrXLHXeRTbtEPzs9hL8lEjcett4nE=; b=zGcNf1+QQKjNHx7FAIeWvH0F1N5Trt+6BP2GmUeoaeQW2OK+IrVslSgPs7ITvA2jRf DLWF8CcOs+bZHBpZZFdmd+rUpDIOWedDz2hDk/NAkQbkRCjt6spZ8c2IZtUHcxmzUfWm Pzd+hC2/r1nEi3e6UosloG3miDd+LEVvYPFlRPxXJ6ri/GyiLUjmf/S4caWz3YU8L9E+ sAPG5ky4zx9+JdW32Ow50iH5JtWLG0bvjN+d7BPfjP9H0qPFPFfq7T+a1v/6dVu5CjOo //tnUiv19GT/j2A3fELNE13h/2Pe2wn6ygz87Ric6+uWvHtfmVgQBiYpjdhSmgfs5pE1 a9Ag== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n9-v6si7708093plp.166.2018.07.06.03.31.42; Fri, 06 Jul 2018 03:31:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932642AbeGFKbl (ORCPT + 30 others); Fri, 6 Jul 2018 06:31:41 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:9158 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932318AbeGFK3P (ORCPT ); Fri, 6 Jul 2018 06:29:15 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 8B0196BC1C80; Fri, 6 Jul 2018 18:29:00 +0800 (CST) Received: from S00293818-DELL1.huawei.com (10.202.226.54) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.382.0; Fri, 6 Jul 2018 18:28:55 +0800 From: Salil Mehta To: CC: , , , , , , , Yunsheng Lin Subject: [PATCH net-next 03/10] net: hns3: Fix for waterline not setting correctly Date: Fri, 6 Jul 2018 11:27:57 +0100 Message-ID: <20180706102804.196-4-salil.mehta@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180706102804.196-1-salil.mehta@huawei.com> References: <20180706102804.196-1-salil.mehta@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.226.54] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yunsheng Lin The HCLGE_RX_PRIV_EN_B is used to tell the firmware whether to update the specific waterline value, if the is not set, the firmware will ignore the value. This patch fixes by setting the HCLGE_RX_PRIV_EN_B even if the updated value is zero. Fixes: 46a3df9f9718 ("net: hns3: Add HNS3 Acceleration Engine & Compatibility Layer Support") Signed-off-by: Yunsheng Lin Signed-off-by: Peng Li Signed-off-by: Salil Mehta --- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) -- 2.7.4 diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index 6fffc69..dae1aa5 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -1834,8 +1834,6 @@ static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, return 0; } -#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0) - static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, struct hclge_pkt_buf_alloc *buf_alloc) { @@ -1863,13 +1861,11 @@ static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, req->tc_wl[j].high = cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); req->tc_wl[j].high |= - cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) << - HCLGE_RX_PRIV_EN_B); + cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); req->tc_wl[j].low = cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); req->tc_wl[j].low |= - cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) << - HCLGE_RX_PRIV_EN_B); + cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); } } @@ -1911,13 +1907,11 @@ static int hclge_common_thrd_config(struct hclge_dev *hdev, req->com_thrd[j].high = cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); req->com_thrd[j].high |= - cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) << - HCLGE_RX_PRIV_EN_B); + cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); req->com_thrd[j].low = cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); req->com_thrd[j].low |= - cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) << - HCLGE_RX_PRIV_EN_B); + cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); } } @@ -1943,14 +1937,10 @@ static int hclge_common_wl_config(struct hclge_dev *hdev, req = (struct hclge_rx_com_wl *)desc.data; req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); - req->com_wl.high |= - cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) << - HCLGE_RX_PRIV_EN_B); + req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); - req->com_wl.low |= - cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) << - HCLGE_RX_PRIV_EN_B); + req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); ret = hclge_cmd_send(&hdev->hw, &desc, 1); if (ret) {