From patchwork Fri Jun 1 11:24:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 137511 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp805273lji; Fri, 1 Jun 2018 04:25:10 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLydraGOtQbgYIJrgU3swuOgOnSam14eJTX3orkRKrQ9C/7dhqsMQB40wagqcAvURTO4Q4h X-Received: by 2002:a62:6a0a:: with SMTP id f10-v6mr10355746pfc.99.1527852310299; Fri, 01 Jun 2018 04:25:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527852310; cv=none; d=google.com; s=arc-20160816; b=YITmZh7IF96T2G0qO8N2y/5qAueInwl4TpNI6wC/jDwtuG+3+POslXK+mNhxUbnAX7 eKrg4X/ltQaG/PbkBNTYp1kveOgUXguoZGQfhxp9mhGsCCmyfygz1/dHAGtrReW6Rzz+ DCg1unjW9nCt2C/QhOAdolAUTYAZUI7U/oZBgYJfCFbQqDfmgdZea5lcf8qwIhvKc4+S d8YTAIN+kNw3DntvBmJP6Fy+oKvcYzqHPEDMYA5siFHxPQ79Vk+ouUJxflEru3om2nP/ zU+H8D9ZDT6cECh8PCq7qJihgfvZOdG67LU9tEx7BELaMOB8ubSCj9CKFrRVc8nAL0RE 0D5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=KhSuPTejIwL3fzpLs2g94019El0zpSTFUIDSdspDH5U=; b=r67ehaZuw39/Wamwei4j3G7MafCF9fDfql+4HmbQ6PFWSlv0SElcghLGN60YUtR0KY 38xsnMJg8D7F6N4WDYWAbeqk0/mqNSCNlWMc2ip+0QLAS073TRGLTwwrUoHoDoIUaqeR RXxGLKekcF3wfZSUuVDuiIWwETimrzsDlYUve87ZRwQDU0RwfLhpN5OUTGVYFx61Pj2s fc48WjzVGw6xMRmnUkMi28+/9ZbWZL5xdnhkzWK1ISi+EYzkFCpGn365Szff0T023Qmm N/VpvKyYo77iByDZwkK6t3NN31nV2Vg7USNTBA+ynmsXp0GLYIRICm3TN7+S8gUX/f7D ysnw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x6-v6si13773302pll.24.2018.06.01.04.25.09; Fri, 01 Jun 2018 04:25:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751981AbeFALZH (ORCPT + 30 others); Fri, 1 Jun 2018 07:25:07 -0400 Received: from foss.arm.com ([217.140.101.70]:50284 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751849AbeFALY4 (ORCPT ); Fri, 1 Jun 2018 07:24:56 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 55B76164F; Fri, 1 Jun 2018 04:24:56 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 24EA13F25D; Fri, 1 Jun 2018 04:24:55 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, will.deacon@arm.com, catalin.marinas@arm.com Cc: Mark Rutland , Marc Zyngier Subject: [PATCHv2 03/19] arm64: introduce sysreg_clear_set() Date: Fri, 1 Jun 2018 12:24:25 +0100 Message-Id: <20180601112441.37810-4-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180601112441.37810-1-mark.rutland@arm.com> References: <20180601112441.37810-1-mark.rutland@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently we have a couple of helpers to manipulate bits in particular sysregs: * config_sctlr_el1(u32 clear, u32 set) * change_cpacr(u64 val, u64 mask) The parameters of these differ in naming convention, order, and size, which is unfortunate. They also differ slightly in behaviour, as change_cpacr() skips the sysreg write if the bits are unchanged, which is a useful optimization when sysreg writes are expensive. Before we gain more yet another sysreg manipulation function, let's unify these with a common helper, providing a consistent order for clear/set operands, and the write skipping behaviour from change_cpacr(). Code will be migrated to the new helper in subsequent patches. Signed-off-by: Mark Rutland Reviewed-by: Dave Martin Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/include/asm/sysreg.h | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.11.0 diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index bd1d1194a5e7..b52762769329 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -729,6 +729,17 @@ asm( asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \ } while (0) +/* + * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the + * set mask are set. Other bits are left as-is. + */ +#define sysreg_clear_set(sysreg, clear, set) do { \ + u64 __scs_val = read_sysreg(sysreg); \ + u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ + if (__scs_new != __scs_val) \ + write_sysreg(__scs_new, sysreg); \ +} while (0) + static inline void config_sctlr_el1(u32 clear, u32 set) { u32 val;