From patchwork Fri Apr 27 12:08:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 134602 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp640886lji; Fri, 27 Apr 2018 05:09:48 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpPZDqzL3tpT94jaVTrDZ6Ke4Av9Pzp1JQaTk/IQpvgvNsAgdIkQggalCrI5S0cFHKns6XS X-Received: by 2002:a65:668f:: with SMTP id b15-v6mr1887105pgw.183.1524830988291; Fri, 27 Apr 2018 05:09:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524830988; cv=none; d=google.com; s=arc-20160816; b=CueEN+teRDi4nzhv5ik4LiYgmzygGxRgS2AZF7m29pNLquPfDrXfcmpVQ3NUZBNvFK QOSOG34kDC2o3OfkFVzFmuVaK4D9eegzMsZBf0dD/jHbGOatOAaRKV/RpBaMXJ4mEfMI g1Z5rqvyPypgNcDilwDusWw1h6jmBwYODIhv6n9dbfYjXhTzgrXJBEeL1xJwykN1SS29 QkiO9P1BvL4C9eqJCdKktY4tCZfg1jiBjNsRMg5wveBewjMztkXK3dK8u2cpyVLDP142 +fXjEGD6BWIRTAY2sKUX4eg0VkfjcBzPAX3sIpiQufMNu95WHd8wrg0n4ECQ+57thHE/ QzuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=GN2G7m+hEckakXGXm8s00j5tg1aekNFku5MOmNRqQBc=; b=kHBqHkdc5clQUikqPvmq8doa5+zsXrNBUES0rMtzdQyn+AMPyV3+QUTpbbNyui60yw fBav5TjPS6Y/ki29dWlleiomPcvMoEivIM9TyhZxkNJW5cnjSqFXPJH3YrUw+sGIruIR j8I4b3e9Zdt13Lu1CQM9aBKp3+MmPZcCCNtR4oihMYdOqZ0olSgd9MkiQt9cLLEn4Fgq UtZ61xCUuMiW7UcvDf1Ps51afjY0+/BnxMpzRp5VH4VMyDy1X/yB/RhaZb6M84x7gjtb lHClBzvYVrund0otodDXHywSc9kqg8vAwHSo1NbvzeY/fCZjXRirH2KTlGq0652TIius bJtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=o0hM7HMt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x1-v6si1173801plb.8.2018.04.27.05.09.47; Fri, 27 Apr 2018 05:09:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=o0hM7HMt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758132AbeD0MJp (ORCPT + 29 others); Fri, 27 Apr 2018 08:09:45 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:47300 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758067AbeD0MJk (ORCPT ); Fri, 27 Apr 2018 08:09:40 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id w3RC9YHP012842; Fri, 27 Apr 2018 07:09:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1524830974; bh=nUIiDVoUbXu4e0l2n7rzSlq1tny3bSScooFQsdfw4rw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=o0hM7HMtkrU3YA60gOCZd7jq50SR4s/K0dUwj2EW5/dytE5synWDAwJMjjCC0KaKn cbQxuAbo8PGGeByxVKwgYC2NokqtgAXwnxMB1KnOQsz++gbJAudmf8DWvWsAsR2nlK 1L/xv7SBn8ZeTJNun495EMpgTV70YZ3lZQCspJ/w= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3RC9YGU017443; Fri, 27 Apr 2018 07:09:34 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 27 Apr 2018 07:09:33 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 27 Apr 2018 07:09:34 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3RC9AjO006789; Fri, 27 Apr 2018 07:09:30 -0500 From: Kishon Vijay Abraham I To: Tony Lindgren CC: Jonathan Corbet , =?utf-8?q?Beno=C3=AEt_Cousson?= , Rob Herring , Mark Rutland , , , , , , Sekhar Nori Subject: [PATCH v4 06/14] ARM: dts: am574x-idk: Add pinmux configuration for MMC Date: Fri, 27 Apr 2018 17:38:57 +0530 Message-ID: <20180427120905.3665-7-kishon@ti.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180427120905.3665-1-kishon@ti.com> References: <20180427120905.3665-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sekhar Nori Include dra76x-mmc-iodelay.dtsi which has pinmux and IODelay configuration values for the various MMC modes for am574x SoC and use it in the pinctrl properties of MMC devicetree nodes present in am574x-idk.dts. Signed-off-by: Sekhar Nori Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/am574x-idk.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.17.0 diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/am574x-idk.dts index 41e12a382d2f..c7718b2d9fdf 100644 --- a/arch/arm/boot/dts/am574x-idk.dts +++ b/arch/arm/boot/dts/am574x-idk.dts @@ -7,6 +7,8 @@ /dts-v1/; #include "dra76x.dtsi" +#include "dra7-mmc-iodelay.dtsi" +#include "dra76x-mmc-iodelay.dtsi" #include "am572x-idk-common.dtsi" / { @@ -20,3 +22,21 @@ spi-max-frequency = <96000000>; }; }; + +&mmc1 { + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_default>; + pinctrl-3 = <&mmc1_pins_hs>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_conf>; + pinctrl-6 = <&mmc1_pins_ddr50 &mmc1_iodelay_sdr104_conf>; +}; + +&mmc2 { + pinctrl-names = "default", "hs", "ddr_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_default>; + pinctrl-2 = <&mmc2_pins_default>; +};