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[209.132.180.67]) by mx.google.com with ESMTP id c6si1163465pfi.102.2018.04.27.05.12.37; Fri, 27 Apr 2018 05:12:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=OM9iOTtb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758256AbeD0MMd (ORCPT + 29 others); Fri, 27 Apr 2018 08:12:33 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:49453 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758023AbeD0MJh (ORCPT ); Fri, 27 Apr 2018 08:09:37 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w3RC9U1c029191; Fri, 27 Apr 2018 07:09:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1524830970; bh=u2BkH0ysClGs56eqeDwsgIrywM0Lu3C9cY0Bk70/6/c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OM9iOTtbKsadUDlB+6AIDwclnJpo6nUZkHDSANH5lIwLrdm87seKgLwoZaAejAMtC drqqEQ1x7bOVCtOYJJ2nSAINTf26x/ZjqZbWeFudBcVyLQjSt8l8EyHwMYvT1oBKxr ws1fA6gb0STCj6d2Aiwxd3tvWv+GnGoAIzXh+Y2w= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3RC9U5T012760; Fri, 27 Apr 2018 07:09:30 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 27 Apr 2018 07:09:30 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 27 Apr 2018 07:09:30 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3RC9AjN006789; Fri, 27 Apr 2018 07:09:27 -0500 From: Kishon Vijay Abraham I To: Tony Lindgren CC: Jonathan Corbet , =?utf-8?q?Beno=C3=AEt_Cousson?= , Rob Herring , Mark Rutland , , , , , Subject: [PATCH v4 05/14] ARM: dts: dra71-evm: Use pinctrl group from dra7-mmc-iodelay.dtsi to select pulldown Date: Fri, 27 Apr 2018 17:38:56 +0530 Message-ID: <20180427120905.3665-6-kishon@ti.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180427120905.3665-1-kishon@ti.com> References: <20180427120905.3665-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org commit 0e43884cca77218d2eccc331396e8 ("ARM: dts: dra71-evm: Select pull down for mmc1_clk line in default mode") modified mmc1_pins_default pinctrl group in dra71-evm.dts to change the CLK line to PIN_INPUT_PULLDOWN. However instead of changing the pinctrl group, use the new pinctrl group "mmc1_pins_default_no_clk_pu" in dra7-mmc-iodelay.dtsi added specifically to be used for CLK line without external pull up. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra71-evm.dts | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) -- 2.17.0 diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts index 64c57d87ca2f..b7aeaeeead3b 100644 --- a/arch/arm/boot/dts/dra71-evm.dts +++ b/arch/arm/boot/dts/dra71-evm.dts @@ -7,6 +7,7 @@ */ #include "dra72-evm-common.dtsi" +#include "dra7-mmc-iodelay.dtsi" #include "dra72x-mmc-iodelay.dtsi" #include @@ -50,19 +51,6 @@ }; }; -&dra7_pmx_core { - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; -}; - &i2c1 { status = "okay"; clock-frequency = <400000>; @@ -187,7 +175,7 @@ &mmc1 { pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; - pinctrl-0 = <&mmc1_pins_default>; + pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; pinctrl-1 = <&mmc1_pins_hs>; pinctrl-2 = <&mmc1_pins_sdr12>; pinctrl-3 = <&mmc1_pins_sdr25>;