From patchwork Fri Apr 27 12:08:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 134616 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp644976lji; Fri, 27 Apr 2018 05:13:25 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqpRNDyLHW8kdYcChQYtGSER4VQ1tjvwsuzioS9SuEuL1l1UxOl5T89AiXoI/k01nEfpB28 X-Received: by 2002:a17:902:da4:: with SMTP id 33-v6mr2132833plv.52.1524831205319; Fri, 27 Apr 2018 05:13:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524831205; cv=none; d=google.com; s=arc-20160816; b=mGPSrkC868HmxwjFeVPjx9lBKT5KDK8HHafdma5UqEKkGwl2epYhCk6bPZIpEKOAkc BBy7dk8o7OfF++yYPIeGtiz9BPLOjn3gPl3l/Ik8RzbldWBYkoTD18keygwVrSXplL+g 6hxWz5bYp5RymXpbG9tHl7lZzCa5Bb8T7aE7p4sl5/yrcNyY2VPqX2qgoypdJsdop5B4 aXTe65oIxqAuO0xNwcfVx9Sd7JwtZ8Ppn8H3kC58fPRdQ8cSVST59etwMB1VTjOvZjd9 l5X5RZFKlQPop5m4pmC1NwZsmqP7vmrxl8KF5eRhNnObsa6aG2poakGmUwVUGwiCMR3T G9kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=P5ANYMrPPfLOxqvfwThHla4iP8pHV9LQMV+UnU9sp34=; b=pqm04Enh/q07PsLXLpOXrXhz4UgQzJAK8Jk4Z/nThrWykYmGIn0nQnAOUu5KADUrcw gaVZ0CC8ZY824emTyqXNbgGljesTv/ACrMP2StwEqn+DRIKhZDLJ6djAjk8syEX4OLLz wC8JVYT/1uKN+ucnJBAQDlC6I3DN4y5RR10MIa6Kjh3vtsdbz7pfJdv8OyarjvXa1tCq lSd+jlcd3lm8HR7haqKHy/WlC1uIE5Fv090amt5DARievRZU4FAqz0TgnfRMmCs1TCe7 9Sds7zISi3xOSNsFZ+c7KYiBnfoCeZ0EzoS6fLYBoHZc+BkO9wk9ZRuNm6k/P2WSrmPF sCLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ng1i2Gag; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h32-v6si1167925pld.170.2018.04.27.05.13.24; Fri, 27 Apr 2018 05:13:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ng1i2Gag; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758223AbeD0MNX (ORCPT + 29 others); Fri, 27 Apr 2018 08:13:23 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:49440 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758022AbeD0MJb (ORCPT ); Fri, 27 Apr 2018 08:09:31 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w3RC9ORm029174; Fri, 27 Apr 2018 07:09:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1524830964; bh=iozhh+fg5zczkCrBrIFd33uVbNejZexxqjRReyMENeI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ng1i2Gags6kaTjCBbBQvXQf9lnLnCdiFbcl7DtQWbX6QRLjehEe8bO5Fbof46MN1s icdG5S0dzAf8tzem7Z2B3zVlsY1yp4HdZ9dqzaufpY+1BfjGP7t7RO/klNCZ9igi3O mpAWELD2Q2Wcwwph4Lg+fx7Aw/DFq8LW3UZ04McQ= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3RC9OV1012666; Fri, 27 Apr 2018 07:09:24 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 27 Apr 2018 07:09:24 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 27 Apr 2018 07:09:24 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3RC9AjL006789; Fri, 27 Apr 2018 07:09:21 -0500 From: Kishon Vijay Abraham I To: Tony Lindgren CC: Jonathan Corbet , =?utf-8?q?Beno=C3=AEt_Cousson?= , Rob Herring , Mark Rutland , , , , , Subject: [PATCH v4 03/14] ARM: dts: dra7-mmc-iodelay: Add a new pinctrl group for clk line without pullup Date: Fri, 27 Apr 2018 17:38:54 +0530 Message-ID: <20180427120905.3665-4-kishon@ti.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180427120905.3665-1-kishon@ti.com> References: <20180427120905.3665-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org During a short period when the bus voltage is switched from 3.3v to 1.8v, (to enumerate UHS mode), the mmc module is disabled and the mmc IO lines are kept in a state according to the programmed pad mux pull type. According to 4.2.4.2 Timing to Switch Signal Voltage in "SD Specifications Part 1 Physical Layer Specification Version 5.00 February 22, 2016", the host should hold CLK low for at least 5ms. In order to keep the card line low during voltage switch, the pad mux of mmc1_clk line should be configured to pull down. Add a new pinctrl group for clock line without pullup to be used in boards where mmc1_clk line is not connected to an external pullup. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7-mmc-iodelay.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 arch/arm/boot/dts/dra7-mmc-iodelay.dtsi -- 2.17.0 diff --git a/arch/arm/boot/dts/dra7-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra7-mmc-iodelay.dtsi new file mode 100644 index 000000000000..aa0947266526 --- /dev/null +++ b/arch/arm/boot/dts/dra7-mmc-iodelay.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MMC IOdelay values for TI's DRA7xx SoCs. + * Copyright (C) 2018 Texas Instruments + * Author: Kishon Vijay Abraham I + */ + +&dra7_pmx_core { + mmc1_pins_default_no_clk_pu: mmc1_pins_default_no_clk_pu { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; +};