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[209.132.180.67]) by mx.google.com with ESMTP id v5si1168777pfd.341.2018.04.27.04.50.32; Fri, 27 Apr 2018 04:50:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cXZZnUlE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758141AbeD0Lu2 (ORCPT + 29 others); Fri, 27 Apr 2018 07:50:28 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:48819 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758062AbeD0Lrx (ORCPT ); Fri, 27 Apr 2018 07:47:53 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w3RBlnFA026223; Fri, 27 Apr 2018 06:47:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1524829669; bh=UWu4oYEE9F7j1rpVRckcBlnswaQckSNJlqa2Vk2rU20=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cXZZnUlEiP4uS/thDLGIeg80qN0vTRR8ObV8vCs95eOItqcGS94lb9S0gS6gS6TWd EqzCwiMjycuqnSEsVvcW6ggvQmBcBwU0iZ8co8YUlaGSsyEdNKdTqwBYr/F+kR3ilt iWcugVEbNBFEF1J6C0tkhNaLpZxfExVHHSup8Izg= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3RBlnp8015004; Fri, 27 Apr 2018 06:47:49 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 27 Apr 2018 06:47:48 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 27 Apr 2018 06:47:48 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3RBlRSK014207; Fri, 27 Apr 2018 06:47:46 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Adrian Hunter CC: Rob Herring , Mark Rutland , , , , , Subject: [PATCH v5 06/14] mmc: sdhci: Add quirk to disable HW timeout Date: Fri, 27 Apr 2018 17:17:15 +0530 Message-ID: <20180427114723.2687-7-kishon@ti.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180427114723.2687-1-kishon@ti.com> References: <20180427114723.2687-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Adrian Hunter Add quirk to disable HW timeout if the requested timeout is more than the maximum obtainable timeout. Also, if the quirk is set and ->get_max_timeout_count() is not implemented, max_busy_timeout is set to zero. Based-on-patch-by: Kishon Vijay Abraham I Signed-off-by: Adrian Hunter Signed-off-by: Kishon Vijay Abraham I --- drivers/mmc/host/sdhci.c | 38 ++++++++++++++++++++++++++++++++++---- drivers/mmc/host/sdhci.h | 5 +++++ 2 files changed, 39 insertions(+), 4 deletions(-) -- 2.17.0 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 0f3cdca3e769..8da118d0d2c4 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -709,12 +709,15 @@ static u32 sdhci_sdma_address(struct sdhci_host *host) return sg_dma_address(host->data->sg); } -static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) +static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd, + bool *too_big) { u8 count; struct mmc_data *data = cmd->data; unsigned target_timeout, current_timeout; + *too_big = true; + /* * If the host controller provides us with an incorrect timeout * value, just skip the check and use 0xE. The hardware may take @@ -768,9 +771,12 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) } if (count >= 0xF) { - DBG("Too large timeout 0x%x requested for CMD%d!\n", - count, cmd->opcode); + if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT)) + DBG("Too large timeout 0x%x requested for CMD%d!\n", + count, cmd->opcode); count = 0xE; + } else { + *too_big = false; } return count; @@ -790,6 +796,16 @@ static void sdhci_set_transfer_irqs(struct sdhci_host *host) sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); } +static void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable) +{ + if (enable) + host->ier |= SDHCI_INT_DATA_TIMEOUT; + else + host->ier &= ~SDHCI_INT_DATA_TIMEOUT; + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); +} + static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) { u8 count; @@ -797,7 +813,17 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) if (host->ops->set_timeout) { host->ops->set_timeout(host, cmd); } else { - count = sdhci_calc_timeout(host, cmd); + bool too_big = false; + + count = sdhci_calc_timeout(host, cmd, &too_big); + + if (too_big && + host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) { + sdhci_set_data_timeout_irq(host, false); + } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) { + sdhci_set_data_timeout_irq(host, true); + } + sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); } } @@ -3616,6 +3642,10 @@ int sdhci_setup_host(struct sdhci_host *host) mmc->max_busy_timeout /= host->timeout_clk; } + if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT && + !host->ops->get_max_timeout_count) + mmc->max_busy_timeout = 0; + mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index c95b0a4a7594..f6555c0f4ad3 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -437,6 +437,11 @@ struct sdhci_host { #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) /* Controller has CRC in 136 bit Command Response */ #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) +/* + * Disable HW timeout if the requested timeout is more than the maximum + * obtainable timeout. + */ +#define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */