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[209.132.180.67]) by mx.google.com with ESMTP id e7-v6si1086961pgf.652.2018.04.27.04.48.56; Fri, 27 Apr 2018 04:48:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=yJmytQ+y; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757983AbeD0LsS (ORCPT + 29 others); Fri, 27 Apr 2018 07:48:18 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:48836 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757530AbeD0LsN (ORCPT ); Fri, 27 Apr 2018 07:48:13 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w3RBm7hw026424; Fri, 27 Apr 2018 06:48:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1524829687; bh=05tX5TsEfAwpx7uiutq4ONRR4zHcBK3+fV6RhYJcUno=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yJmytQ+yW/2g0U7qkrwbdG1haEG+wJoFBrriZXUhkW1wOB6/0+yWgCs/uPIbzPI21 ZFkkEXUke2LaaNZmU7KfGa4Tg1hJDPWhUBCmh9p5XUkE/NxXxozsuK5R/mdmpjCdVG JpcDD3+DeqirkjESTQPBM6WyfBRd+6gfSEN8/oRk= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3RBm7qa015520; Fri, 27 Apr 2018 06:48:07 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 27 Apr 2018 06:48:06 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 27 Apr 2018 06:48:07 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3RBlRSQ014207; Fri, 27 Apr 2018 06:48:04 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Adrian Hunter CC: Rob Herring , Mark Rutland , , , , , Subject: [PATCH v5 12/14] mmc: sdhci-omap: Add sdhci_omap specific ops for enable_sdio_irq Date: Fri, 27 Apr 2018 17:17:21 +0530 Message-ID: <20180427114723.2687-13-kishon@ti.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180427114723.2687-1-kishon@ti.com> References: <20180427114723.2687-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add sdhci_omap_enable_sdio_irq to set CTPL and CLKEXTFREE bits in MMCHS_CON register required to detect asynchronous card interrupt on DAT[1]. Signed-off-by: Kishon Vijay Abraham I Acked-by: Adrian Hunter Acked-by: Tony Lindgren --- drivers/mmc/host/sdhci-omap.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) -- 2.17.0 diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c index b11c846dd8a1..bd5e03d177e0 100644 --- a/drivers/mmc/host/sdhci-omap.c +++ b/drivers/mmc/host/sdhci-omap.c @@ -36,6 +36,7 @@ #define CON_DDR BIT(19) #define CON_CLKEXTFREE BIT(16) #define CON_PADEN BIT(15) +#define CON_CTPL BIT(11) #define CON_INIT BIT(1) #define CON_OD BIT(0) @@ -226,6 +227,23 @@ static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host, } } +static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); + u32 reg; + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); + if (enable) + reg |= (CON_CTPL | CON_CLKEXTFREE); + else + reg &= ~(CON_CTPL | CON_CLKEXTFREE); + sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); + + sdhci_enable_sdio_irq(mmc, enable); +} + static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host, int count) { @@ -962,6 +980,7 @@ static int sdhci_omap_probe(struct platform_device *pdev) host->mmc_host_ops.set_ios = sdhci_omap_set_ios; host->mmc_host_ops.card_busy = sdhci_omap_card_busy; host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning; + host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq; ret = sdhci_setup_host(host); if (ret)