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[209.132.180.67]) by mx.google.com with ESMTP id p6si2127997pgq.657.2018.04.18.19.52.54; Wed, 18 Apr 2018 19:52:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=ZrHo7sYA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753120AbeDSCwv (ORCPT + 29 others); Wed, 18 Apr 2018 22:52:51 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:44402 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751878AbeDSCwt (ORCPT ); Wed, 18 Apr 2018 22:52:49 -0400 Received: by mail-pl0-f65.google.com with SMTP id s13-v6so2308211plq.11; Wed, 18 Apr 2018 19:52:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=WoobTd/ZfMruhLiDy+AeMhVt1OiD04iDN2ou9EeHxKk=; b=ZrHo7sYAPuv7e3LNOHwc7uczcfoK08botb5nwOI39zCCIyuEITp2s2QoUDOUVXp41A QFaO8zXa2vY5AIlqrJw9skRcLcRV5AbJayVqPvI3E8LsUAntXLB9sJTDP3Std+WB3qyU vfr7tpHCmXQHuGWXmeS2MdhgFefmKJ/2iUNMyu8DOGRdyoKtbkoSGsuepiNb2I/QHDT8 d9Q2LD8CiZdGnAjxxLoNKO/roLpFzAvP2whVfq5NnFuQ2HgiVc7g2CpIEJXuQ7jIVD53 RHeYw3Fl4dgwfSgWYCknc9HQtr7dHh63aUpGLGw74mpi5J0iFd202+y1CuDVHYpbwfoD rh6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=WoobTd/ZfMruhLiDy+AeMhVt1OiD04iDN2ou9EeHxKk=; b=C8VbupWFSV6ueOOMYNpt/kahOm6MOqCMDaAYoN2S3kYtYh+R59wv0WLfv+kLCVVYeT g8y9wghef/ZZ53/Kn1nplWSfDhfoGgCeKvdzznvpkdMZpWvCPAJWjsGiwaBShht1j+iH PLcI2ho2MmetKsjf6DfmGp0CAOioU9+5Bc7ShEa4wV4Ua14t0PLPpuGiZpX2eSXupu73 o1wwMcj+j0NJEgr3Y7QSFqb8t5KOfMhog3VC0M/hGhp84eCEcEOj2IKBYCYpF4CxvYKL ECBj9Q/VQXeKFL+A3zz0nQ6wGMFk5cCo3HOmvzsPAdzpOqNMHu+dHcwE/nBckyBwF80Q bn/g== X-Gm-Message-State: ALQs6tBNKtN97CV/utnUCmsHoMIaf+dXWXsatUqpCgttwJ9qdh8eKy5e ecaUzr7CL0osxPWpEuLCskM= X-Received: by 2002:a17:902:988b:: with SMTP id s11-v6mr4323653plp.306.1524106368550; Wed, 18 Apr 2018 19:52:48 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id b78sm5935739pfj.6.2018.04.18.19.52.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Apr 2018 19:52:47 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Thu, 19 Apr 2018 12:22:40 +0930 From: Joel Stanley To: Michael Turquette , Stephen Boyd Cc: Andrew Jeffery , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, Ryan Chen Subject: [PATCH] clk: aspeed: Support second reset register Date: Thu, 19 Apr 2018 12:22:40 +0930 Message-Id: <20180419025240.10101-1-joel@jms.id.au> X-Mailer: git-send-email 2.17.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ast2500 has an additional reset register that contains resets not present in the ast2400. This enables support for this register, and adds the one reset line that is controlled by it. Signed-off-by: Joel Stanley --- drivers/clk/clk-aspeed.c | 44 +++++++++++++++++++----- include/dt-bindings/clock/aspeed-clock.h | 1 + 2 files changed, 37 insertions(+), 8 deletions(-) -- 2.17.0 Reviewed-by: Andrew Jeffery diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 5eb50c31e455..93d1dae96624 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -16,6 +16,8 @@ #define ASPEED_NUM_CLKS 35 +#define ASPEED_RESET2_OFFSET 32 + #define ASPEED_RESET_CTRL 0x04 #define ASPEED_CLK_SELECTION 0x08 #define ASPEED_CLK_STOP_CTRL 0x0c @@ -30,6 +32,7 @@ #define CLKIN_25MHZ_EN BIT(23) #define AST2400_CLK_SOURCE_SEL BIT(18) #define ASPEED_CLK_SELECTION_2 0xd8 +#define ASPEED_RESET_CTRL2 0xd4 /* Globally visible clocks */ static DEFINE_SPINLOCK(aspeed_clk_lock); @@ -291,6 +294,7 @@ struct aspeed_reset { #define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) static const u8 aspeed_resets[] = { + /* SCU04 resets */ [ASPEED_RESET_XDMA] = 25, [ASPEED_RESET_MCTP] = 24, [ASPEED_RESET_ADC] = 23, @@ -300,38 +304,62 @@ static const u8 aspeed_resets[] = { [ASPEED_RESET_PCIVGA] = 8, [ASPEED_RESET_I2C] = 2, [ASPEED_RESET_AHB] = 1, + + /* + * SCUD4 resets start at an offset to separate them from + * the SCU04 resets. + */ + [ASPEED_RESET_CRT1] = ASPEED_RESET2_OFFSET + 5, }; static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { struct aspeed_reset *ar = to_aspeed_reset(rcdev); - u32 rst = BIT(aspeed_resets[id]); + u32 reg = ASPEED_RESET_CTRL; + u32 bit = aspeed_resets[id]; + + if (bit >= ASPEED_RESET2_OFFSET) { + bit -= ASPEED_RESET2_OFFSET; + reg = ASPEED_RESET_CTRL2; + } - return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0); + return regmap_update_bits(ar->map, reg, BIT(bit), 0); } static int aspeed_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) { struct aspeed_reset *ar = to_aspeed_reset(rcdev); - u32 rst = BIT(aspeed_resets[id]); + u32 reg = ASPEED_RESET_CTRL; + u32 bit = aspeed_resets[id]; - return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst); + if (bit >= ASPEED_RESET_CTRL2) { + bit -= ASPEED_RESET2_OFFSET; + reg = ASPEED_RESET_CTRL2; + } + + return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit)); } static int aspeed_reset_status(struct reset_controller_dev *rcdev, unsigned long id) { struct aspeed_reset *ar = to_aspeed_reset(rcdev); - u32 val, rst = BIT(aspeed_resets[id]); - int ret; + u32 reg = ASPEED_RESET_CTRL; + u32 bit = aspeed_resets[id]; + int ret, val; + + if (bit >= ASPEED_RESET2_OFFSET) { + bit -= ASPEED_RESET2_OFFSET; + reg = ASPEED_RESET_CTRL2; + } - ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val); + ret = regmap_read(ar->map, reg, &val); if (ret) return ret; - return !!(val & rst); + return !!(val & BIT(bit)); } static const struct reset_control_ops aspeed_reset_ops = { diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index d3558d897a4d..513c1b4af7a8 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -48,5 +48,6 @@ #define ASPEED_RESET_PCIVGA 6 #define ASPEED_RESET_I2C 7 #define ASPEED_RESET_AHB 8 +#define ASPEED_RESET_CRT1 9 #endif