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Sun, 8 Apr 2018 20:39:19 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=3CsGGYx3UZA0JDYv59+IeM6eL5AWmAw5uJHtyZGlZQ0=; b=WKLHT+sWF6HGkI3xMApusCxmX8LujEW3E5yypJRsU5h+gUKaYPEzDXmEISfjm6a/gP673JGr3wCI39/jn6n+8iUjzy0T+1kvNorFViu+aPY6nWEwVRkjIQT2MJVvfW/+FvitLjU+kHYlClRx4WauyhSW4K+knScubP8L3Y6O/Lk= Received: from DM5PR2101MB1032.namprd21.prod.outlook.com (52.132.128.13) by DM5PR2101MB1125.namprd21.prod.outlook.com (52.132.130.150) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.696.0; Mon, 9 Apr 2018 00:39:18 +0000 Received: from DM5PR2101MB1032.namprd21.prod.outlook.com ([fe80::8109:aef0:a777:7059]) by DM5PR2101MB1032.namprd21.prod.outlook.com ([fe80::8109:aef0:a777:7059%2]) with mapi id 15.20.0696.003; Mon, 9 Apr 2018 00:39:18 +0000 From: Sasha Levin To: "stable@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: Will Deacon , Catalin Marinas , Sasha Levin Subject: [PATCH AUTOSEL for 4.4 152/162] arm64: spinlock: Fix theoretical trylock() A-B-A with LSE atomics Thread-Topic: [PATCH AUTOSEL for 4.4 152/162] arm64: spinlock: Fix theoretical trylock() A-B-A with LSE atomics Thread-Index: AQHTz5ndWKyNBLBiO0KmDVG9mTfa6w== Date: Mon, 9 Apr 2018 00:29:48 +0000 Message-ID: <20180409002738.163941-152-alexander.levin@microsoft.com> References: <20180409002738.163941-1-alexander.levin@microsoft.com> In-Reply-To: <20180409002738.163941-1-alexander.levin@microsoft.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [52.168.54.252] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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DIR:OUT; SFP:1102; SCL:1; SRVR:DM5PR2101MB1125; H:DM5PR2101MB1032.namprd21.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: microsoft.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: AtGrAFekcxKhLAPdEX2lPn/NyDDCYpAVc8suW4uLMW6Ernh3bb/gwQ3/FlpURu9My5/M26EWLRrf6KYlwawK1w0xwKtkKZXbofhBvF6eeoJEvV/7kp1g5wU2e7ewzeIbR83o2MhDrvcqb6/Jj8bAkbKfPhwhcyv0vEf+dwEQv/P8nBpNT/pwCmptzsdb4GrLj3iXOEYkaOvDFY69LiyIiFfq2SbMMSlAuo4kAyrms1AQ5xKPzkK96dOdQJeWksIg9n8EJqFBRezjrt95PgymGzyTe2Jx1sH0I+rvIRZ3rD1gu0DBdZePd7u2goXoZeeM+MxJweK16Q7VbfKvaEXIb1hRn+8Y7DkntVaOjH2D7m+9akYD9tPYJ8vyTZm2tvVYcj8dEKPMWI5YJlIH6BZ8L+JzNUanis6gjQbQxjRSH9w= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: e720bffb-60f3-4df4-6f7d-08d59db2542e X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2018 00:29:48.6933 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR2101MB1125 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Will Deacon [ Upstream commit 202fb4ef81e3ec765c23bd1e6746a5c25b797d0e ] If the spinlock "next" ticket wraps around between the initial LDR and the cmpxchg in the LSE version of spin_trylock, then we can erroneously think that we have successfuly acquired the lock because we only check whether the next ticket return by the cmpxchg is equal to the owner ticket in our updated lock word. This patch fixes the issue by performing a full 32-bit check of the lock word when trying to determine whether or not the CASA instruction updated memory. Reported-by: Catalin Marinas Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Sasha Levin --- arch/arm64/include/asm/spinlock.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.15.1 diff --git a/arch/arm64/include/asm/spinlock.h b/arch/arm64/include/asm/spinlock.h index 499e8de33a00..fbbd7fb83fd6 100644 --- a/arch/arm64/include/asm/spinlock.h +++ b/arch/arm64/include/asm/spinlock.h @@ -94,8 +94,8 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock) " cbnz %w1, 1f\n" " add %w1, %w0, %3\n" " casa %w0, %w1, %2\n" - " and %w1, %w1, #0xffff\n" - " eor %w1, %w1, %w0, lsr #16\n" + " sub %w1, %w1, %3\n" + " eor %w1, %w1, %w0\n" "1:") : "=&r" (lockval), "=&r" (tmp), "+Q" (*lock) : "I" (1 << TICKET_SHIFT)