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[209.132.180.67]) by mx.google.com with ESMTP id f35-v6si3508098plh.691.2018.04.04.10.24.53; Wed, 04 Apr 2018 10:24:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BR72pd+Z; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751519AbeDDRYv (ORCPT + 29 others); Wed, 4 Apr 2018 13:24:51 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:44127 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750890AbeDDRYp (ORCPT ); Wed, 4 Apr 2018 13:24:45 -0400 Received: by mail-pl0-f65.google.com with SMTP id b6-v6so13009161pla.11 for ; Wed, 04 Apr 2018 10:24:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jLdZFBFUyckKPEbJXNCeaJgwrec114GPO6CefOxXRBk=; b=BR72pd+Z/vhjELOkKgFICVRzjT4V1T8EPUl0ZbUu6gq2Qpb/MFSULj7GbuN6dQg9H0 3iKaY19zGH7JIty7D4agKEKMXIcNnjqZcylWixJPkRs1UIiOEVOMYJixf+Lwy2OMRht/ GGi125fCf/mkRHCBALvqtFY/B63M1uD23fGow= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jLdZFBFUyckKPEbJXNCeaJgwrec114GPO6CefOxXRBk=; b=sTAks1IBrIeTRpXM34MkDjAAi+wG8eNK6kNw8p+JoShxQnCzeg1ejgUjn4Kqg2FU0j JKvkx6am3j5SDznRJjNqDkuqhWpkk8i7eUJcOPqqyyDMizTnOhM8cNV+2p85gZSX15zG CjDIsA1FpcGXQqiYeu6IsE/NjqN3zScKHL4jROD/zN93g3QTTacQ3HAnuiYNsdb28G9T cDMK7QpgBXEf60OGFyyWA6mqO5we7ApHuw9cTXjbT8VSBWrE3DY8cILDbi3PqoNxfxMk iQ58upowbrGdHBr9glayH0h5U/rLFcYf9B4XGaIWRsGGFKIsUCk0NmhMGraqHayAOYVK D2mA== X-Gm-Message-State: AElRT7EZ7jnu7HgLUzB7xD8igzHRDPbW5Ss3j8SrJTHM8rF6dk4yBvhA HIbwjKlqtdsdoqPHjcRcSs1F X-Received: by 2002:a17:902:6a89:: with SMTP id n9-v6mr19707620plk.51.1522862684603; Wed, 04 Apr 2018 10:24:44 -0700 (PDT) Received: from localhost.localdomain ([2405:204:730d:2b78:a8cb:9f26:6eed:eba5]) by smtp.gmail.com with ESMTPSA id t5sm10791384pgr.69.2018.04.04.10.24.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Apr 2018 10:24:44 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org, afaerber@suse.de Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v7 4/9] dt-bindings: gpio: Add gpio nodes for Actions S900 SoC Date: Wed, 4 Apr 2018 22:52:53 +0530 Message-Id: <20180404172258.7678-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180404172258.7678-1-manivannan.sadhasivam@linaro.org> References: <20180404172258.7678-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add gpio nodes for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/gpio/actions,owl-gpio.txt | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/actions,owl-gpio.txt -- 2.14.1 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/gpio/actions,owl-gpio.txt b/Documentation/devicetree/bindings/gpio/actions,owl-gpio.txt new file mode 100644 index 000000000000..34283e9195ea --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/actions,owl-gpio.txt @@ -0,0 +1,87 @@ +* Actions Semi OWL GPIO controller bindings + +The GPIOs are organized as individual banks/ports with variable number +of GPIOs. Each bank is represented as an individual GPIO controller. + +Required properties: +- compatible : Should be "actions,s900-gpio" +- reg : Address and range of the GPIO controller registers. +- gpio-controller : Marks the device node as a GPIO controller. +- #gpio-cells : Should be <2>. The first cell is the gpio number + and the second cell is used to specify optional + parameters. +- ngpios : Specifies the number of GPIO lines. +- interrupt-controller : Marks the device node as an interrupt controller. +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt. Shall be set to 2. The first cell + defines the interrupt number, the second encodes + the trigger flags described in + bindings/interrupt-controller/interrupts.txt + +Optional properties: +- gpio-ranges : Mapping between GPIO and pinctrl + +Examples: + + gpioa: gpio@e01b0000 { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b0000 0x0 0x000c>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpiob: gpio@e01b000c { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b000c 0x0 0x000c>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpioc: gpio@e01b0018 { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b0018 0x0 0x000c>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 12>; + ngpios = <12>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpiod: gpio@e01b0024 { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b0024 0x0 0x000c>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 76 30>; + ngpios = <30>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpioe: gpio@e01b0030 { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b0030 0x0 0x000c>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 106 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpiof: gpio@e01b00f0 { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b00f0 0x0 0x000c>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 138 8>; + ngpios = <8>; + interrupt-controller; + #interrupt-cells = <2>; + };