From patchwork Mon Mar 26 17:38:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 132427 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp4116714ljb; Mon, 26 Mar 2018 10:42:14 -0700 (PDT) X-Google-Smtp-Source: AG47ELt0mmuuWxrzTxTRKZLc1hBt/SxdHbBrHXlm9zwMuDJ5d85oLmkJZOV3sderB4ZVddqBKGe0 X-Received: by 10.98.86.16 with SMTP id k16mr11194650pfb.149.1522086134208; Mon, 26 Mar 2018 10:42:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522086134; cv=none; d=google.com; s=arc-20160816; b=gxlMWO74z0XUtBF2cJDSsl/3tu+1CVJlOPAE35JHLHxp9TxpFBZvbth1YV3cPhS79T Zpc+U3dPR1i15MbsEo9suZ3bnvAwGFlWnpMFa4DK3PvLDdm0RO9NnTbdMNBtQFcBYywR kHac1Fw3appMvyf3Edxj0424xfJuu8FEqylZ6H92vQB+s4Scoi1J1KB0TPP1tcKyFMao p4V/iE6KQpv/KOuPcxaPiodpEDsarDwTslEOzxL2B7nksWr9U5JYKI7e8uAeEaffc1oJ IPGewt+X9CKYnTNFyHSRLsG9RFWgXG1RwNADUmGCyc0fVhF3YZZQePXrU3QfQ7WfBcRG HHvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=ydDB2V3AyQEtvrDuSv1lHnKyLY+7lvHldAQ1/HedKuo=; b=y8CY8459oNMdADCH3AyaPM4bXTNcwzrKp3emhytleAXSRfBqbQH4nQsFJmcVKg9/HZ 8KKQ/Zq3us92MCReSEIEZhVJ341PzSfoRdN4brPYijUBCoxnorAq7aenPcKOV4UCu912 HCR83blYKI9oOiqNdIi3oko8qjnnMMQdFZmU+Z4YexgDPCY6RBjDW1sfDrB32wnF8x+0 AYhm7K/v0QP6rKBcpZScNh1wFb6VPDpikgcdbOU4CmRfHv9bSG5oEohDsesyb69crE4S CUNTIWMT7vM7Ou7Am2GWiX50Ixxl+kyVOQmFI+Hy7l+H6jU/hUjOh5twUqkfDOeQtGbm cPdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X/qoxqZ+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s10si10417341pgp.162.2018.03.26.10.42.13; Mon, 26 Mar 2018 10:42:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X/qoxqZ+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752872AbeCZRmM (ORCPT + 28 others); Mon, 26 Mar 2018 13:42:12 -0400 Received: from mail-pg0-f67.google.com ([74.125.83.67]:37895 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752852AbeCZRmK (ORCPT ); Mon, 26 Mar 2018 13:42:10 -0400 Received: by mail-pg0-f67.google.com with SMTP id a15so7546495pgn.5 for ; Mon, 26 Mar 2018 10:42:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ydDB2V3AyQEtvrDuSv1lHnKyLY+7lvHldAQ1/HedKuo=; b=X/qoxqZ+CwqBPykauFi+R7anzrnGVIs3awCUM3KoLf+jcouQFpuC9pMcDYWYTBLib0 lNhnRi1SJXH9Xw7JI0n1LLAmiKlwY5s34cAbN8M6Xr1wqBH/J6yToMJtiQWaLAUIp86R 0N70ka5YKWIbNTF3wMV8hbm+RD/LD6tLTYre8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ydDB2V3AyQEtvrDuSv1lHnKyLY+7lvHldAQ1/HedKuo=; b=DpVscq1KY2DE6k33B0S/l9voXUEv8wP5AOFd9/fuKW/67tH4L2nT2HphEpMn6y5FEV nvGCDbvBcTPMUH+z1IwQ8t6Gm2KbuRPE61avRnY/AbkVhchShnt0gLWJAjNeyO0atDb2 hvOY1vVcNkMfNzMPHMWNAkGiAxg+E/NRJv0VBqvA/rfSQbxR8a1peMuFO4MrOFcVZ9Vj MUteHSH3Ruz3OS9qftmfsEF9A7tL5Wqm8BrBU7UuNdbIgdGD0M8faWT/7ZqnEIGZROEI E1/k3PCnznpckotskhzNA8f/ptWOIkmDAIIFLGJrrrNbY1oHOBX9mUMnAuMRds7OeuCu UgXw== X-Gm-Message-State: AElRT7G5erzC+Fb03M+/ciQ1e1n0ZUUHaNN9axe8ovw6aJE3jrPXGf0u sa1oiXQixxBi1Z8AA4NVKb1Z X-Received: by 10.98.11.149 with SMTP id 21mr920996pfl.64.1522086129371; Mon, 26 Mar 2018 10:42:09 -0700 (PDT) Received: from localhost.localdomain ([2405:204:73cc:afee:304e:6518:873b:59b1]) by smtp.gmail.com with ESMTPSA id x14sm24986115pgo.82.2018.03.26.10.41.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 26 Mar 2018 10:42:08 -0700 (PDT) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, viresh.kumar@linaro.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v7 04/11] clk: actions: Add gate clock support Date: Mon, 26 Mar 2018 23:08:58 +0530 Message-Id: <20180326173905.22313-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180326173905.22313-1-manivannan.sadhasivam@linaro.org> References: <20180326173905.22313-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for Actions Semi gate clock together with helper functions to be used in composite clock. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/actions/Makefile | 1 + drivers/clk/actions/owl-gate.c | 77 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/actions/owl-gate.h | 73 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 151 insertions(+) create mode 100644 drivers/clk/actions/owl-gate.c create mode 100644 drivers/clk/actions/owl-gate.h -- 2.14.1 diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile index 64a50fc2d335..1f0917872c9d 100644 --- a/drivers/clk/actions/Makefile +++ b/drivers/clk/actions/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_CLK_ACTIONS) += clk-owl.o clk-owl-y += owl-common.o +clk-owl-y += owl-gate.o diff --git a/drivers/clk/actions/owl-gate.c b/drivers/clk/actions/owl-gate.c new file mode 100644 index 000000000000..f11500ba46a7 --- /dev/null +++ b/drivers/clk/actions/owl-gate.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL gate clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#include +#include + +#include "owl-gate.h" + +void owl_gate_set(const struct owl_clk_common *common, + const struct owl_gate_hw *gate_hw, bool enable) +{ + int set = gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; + u32 reg; + + set ^= enable; + + regmap_read(common->regmap, gate_hw->reg, ®); + + if (set) + reg |= BIT(gate_hw->bit_idx); + else + reg &= ~BIT(gate_hw->bit_idx); + + regmap_write(common->regmap, gate_hw->reg, reg); +} + +static void owl_gate_disable(struct clk_hw *hw) +{ + struct owl_gate *gate = hw_to_owl_gate(hw); + struct owl_clk_common *common = &gate->common; + + owl_gate_set(common, &gate->gate_hw, false); +} + +static int owl_gate_enable(struct clk_hw *hw) +{ + struct owl_gate *gate = hw_to_owl_gate(hw); + struct owl_clk_common *common = &gate->common; + + owl_gate_set(common, &gate->gate_hw, true); + + return 0; +} + +int owl_gate_clk_is_enabled(const struct owl_clk_common *common, + const struct owl_gate_hw *gate_hw) +{ + u32 reg; + + regmap_read(common->regmap, gate_hw->reg, ®); + + if (gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE) + reg ^= BIT(gate_hw->bit_idx); + + return !!(reg & BIT(gate_hw->bit_idx)); +} + +static int owl_gate_is_enabled(struct clk_hw *hw) +{ + struct owl_gate *gate = hw_to_owl_gate(hw); + struct owl_clk_common *common = &gate->common; + + return owl_gate_clk_is_enabled(common, &gate->gate_hw); +} + +const struct clk_ops owl_gate_ops = { + .disable = owl_gate_disable, + .enable = owl_gate_enable, + .is_enabled = owl_gate_is_enabled, +}; diff --git a/drivers/clk/actions/owl-gate.h b/drivers/clk/actions/owl-gate.h new file mode 100644 index 000000000000..c2d61ceebce2 --- /dev/null +++ b/drivers/clk/actions/owl-gate.h @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL gate clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#ifndef _OWL_GATE_H_ +#define _OWL_GATE_H_ + +#include "owl-common.h" + +struct owl_gate_hw { + u32 reg; + u8 bit_idx; + u8 gate_flags; +}; + +struct owl_gate { + struct owl_gate_hw gate_hw; + struct owl_clk_common common; +}; + +#define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ + { \ + .reg = _reg, \ + .bit_idx = _bit_idx, \ + .gate_flags = _gate_flags, \ + } + +#define OWL_GATE(_struct, _name, _parent, _reg, \ + _bit_idx, _gate_flags, _flags) \ + struct owl_gate _struct = { \ + .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT(_name, \ + _parent, \ + &owl_gate_ops, \ + _flags), \ + } \ + } \ + +#define OWL_GATE_NO_PARENT(_struct, _name, _reg, \ + _bit_idx, _gate_flags, _flags) \ + struct owl_gate _struct = { \ + .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT_NO_PARENT(_name, \ + &owl_gate_ops, \ + _flags), \ + }, \ + } \ + +static inline struct owl_gate *hw_to_owl_gate(const struct clk_hw *hw) +{ + struct owl_clk_common *common = hw_to_owl_clk_common(hw); + + return container_of(common, struct owl_gate, common); +} + +void owl_gate_set(const struct owl_clk_common *common, + const struct owl_gate_hw *gate_hw, bool enable); +int owl_gate_clk_is_enabled(const struct owl_clk_common *common, + const struct owl_gate_hw *gate_hw); + +extern const struct clk_ops owl_gate_ops; + +#endif /* _OWL_GATE_H_ */