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[209.132.180.67]) by mx.google.com with ESMTP id 61-v6si7784735plr.136.2018.03.17.03.11.43; Sat, 17 Mar 2018 03:11:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TXLW35lb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752565AbeCQKLh (ORCPT + 28 others); Sat, 17 Mar 2018 06:11:37 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:43375 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752464AbeCQKLd (ORCPT ); Sat, 17 Mar 2018 06:11:33 -0400 Received: by mail-pg0-f65.google.com with SMTP id e9so5057729pgs.10 for ; Sat, 17 Mar 2018 03:11:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SQGyxKuKh7kk1DTIAS5AB/WGlPSeIM69CRcjILG6EAg=; b=TXLW35lbiuKTFCyeTtM+izjBBQJv42lEW6uYjCZMZhrBvkWQhtF9SO4f4972OUKnh8 p+uduRKVmc4cRe7+A3LyUVgeIxc9nRBJ/LgV2UHpfdwryw1Vzok6LoTfYVmoxk/YnBnm vAO7fSN6XnZU+BP3WT3cqFuPTRzA4U9tcDYiE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SQGyxKuKh7kk1DTIAS5AB/WGlPSeIM69CRcjILG6EAg=; b=N+9CWxzX8a5egDgzwJuYKi+AWQI/WXrg9AxkFqe6yQiDdKOFUXfRyjUaSpAv6TFAaX fQxumJVaOc+XnpcuwIeqczT42JUefNVp6r42PtMMB1Q4SXF0PUjC7UFB4MQHltg3oky1 d+Zx1nJq7nMDfsjGqnhx8Sou45X3jwJ7ljyYFT4fkxUoz2WmP0C9ms3mL3M4l0apQf9s yFwvsxWi9jGcPgQkZi92TpxGVVh+CfYVHKfs01Ato/PikbTgr896N7urfVNCmMc8f/Xh JSPs6nOUeyCCcArdKipKW8XNp/TP2SN7tpYbyl7FXZGgemGAIQeR/BQZAkA0kUxny0r7 mkuw== X-Gm-Message-State: AElRT7HOIpimV/RtC8S96xq590lxZDeWmkBw7QQe8ULNAYEPCnVwEBEg ON7xFqGSTvgcJme/0OWSpzap X-Received: by 10.99.176.12 with SMTP id h12mr3095858pgf.448.1521281492316; Sat, 17 Mar 2018 03:11:32 -0700 (PDT) Received: from mani-Aspire-E5-573.domain.name ([171.49.203.57]) by smtp.gmail.com with ESMTPSA id i27sm3771625pfj.123.2018.03.17.03.11.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 17 Mar 2018 03:11:31 -0700 (PDT) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, viresh.kumar@linaro.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v5 04/12] clk: actions: Add common clock driver support Date: Sat, 17 Mar 2018 15:39:44 +0530 Message-Id: <20180317100952.28538-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180317100952.28538-1-manivannan.sadhasivam@linaro.org> References: <20180317100952.28538-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for Actions Semi common clock driver with generic structures and interface functions. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/actions/Kconfig | 4 ++ drivers/clk/actions/Makefile | 3 ++ drivers/clk/actions/owl-common.c | 84 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/actions/owl-common.h | 41 ++++++++++++++++++++ 6 files changed, 134 insertions(+) create mode 100644 drivers/clk/actions/Kconfig create mode 100644 drivers/clk/actions/Makefile create mode 100644 drivers/clk/actions/owl-common.c create mode 100644 drivers/clk/actions/owl-common.h -- 2.14.1 diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 98ce9fc6e6c0..6313a4f4327a 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -238,6 +238,7 @@ config COMMON_CLK_VC5 This driver supports the IDT VersaClock 5 and VersaClock 6 programmable clock generators. +source "drivers/clk/actions/Kconfig" source "drivers/clk/bcm/Kconfig" source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/imgtec/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 71ec41e6364f..b7909df532ed 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o # please keep this section sorted lexicographically by directory path name +obj-y += actions/ obj-$(CONFIG_COMMON_CLK_AT91) += at91/ obj-$(CONFIG_ARCH_ARTPEC) += axis/ obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/ diff --git a/drivers/clk/actions/Kconfig b/drivers/clk/actions/Kconfig new file mode 100644 index 000000000000..13a3e5083d43 --- /dev/null +++ b/drivers/clk/actions/Kconfig @@ -0,0 +1,4 @@ +config CLK_ACTIONS + bool "Clock driver for Actions Semi SoCs" + depends on ARCH_ACTIONS || COMPILE_TEST + default ARCH_ACTIONS diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile new file mode 100644 index 000000000000..64a50fc2d335 --- /dev/null +++ b/drivers/clk/actions/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_CLK_ACTIONS) += clk-owl.o + +clk-owl-y += owl-common.o diff --git a/drivers/clk/actions/owl-common.c b/drivers/clk/actions/owl-common.c new file mode 100644 index 000000000000..a7cb698fdc86 --- /dev/null +++ b/drivers/clk/actions/owl-common.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL common clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#include +#include +#include + +#include "owl-common.h" + +static const struct regmap_config owl_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xffff, + .fast_io = true, +}; + +static void owl_clk_set_regmap(const struct owl_clk_desc *desc, + struct regmap *regmap) +{ + int i; + struct owl_clk_common *clks; + + for (i = 0; i < desc->num_clks; i++) { + clks = desc->clks[i]; + if (!clks) + continue; + + clks->regmap = regmap; + } +} + +int owl_clk_regmap_init(struct platform_device *pdev, + const struct owl_clk_desc *desc) +{ + void __iomem *base; + struct device_node *node = pdev->dev.of_node; + struct regmap *regmap; + + base = of_iomap(node, 0); + regmap = devm_regmap_init_mmio(&pdev->dev, base, &owl_regmap_config); + if (IS_ERR_OR_NULL(regmap)) { + pr_err("failed to init regmap\n"); + return PTR_ERR(regmap); + } + + owl_clk_set_regmap(desc, regmap); + + return 0; +} + +int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks) +{ + int i, ret; + struct clk_hw *hw; + + for (i = 0; i < hw_clks->num; i++) { + + hw = hw_clks->hws[i]; + + if (!hw) + continue; + + ret = devm_clk_hw_register(dev, hw); + if (ret) { + dev_err(dev, "Couldn't register clock %d - %s\n", + i, hw->init->name); + return ret; + } + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_clks); + if (ret) + dev_err(dev, "Failed to add clock provider\n"); + + return ret; +} diff --git a/drivers/clk/actions/owl-common.h b/drivers/clk/actions/owl-common.h new file mode 100644 index 000000000000..4fd726ec54a6 --- /dev/null +++ b/drivers/clk/actions/owl-common.h @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL common clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#ifndef _OWL_COMMON_H_ +#define _OWL_COMMON_H_ + +#include +#include +#include + +struct device_node; + +struct owl_clk_common { + struct regmap *regmap; + struct clk_hw hw; +}; + +struct owl_clk_desc { + struct owl_clk_common **clks; + unsigned long num_clks; + struct clk_hw_onecell_data *hw_clks; +}; + +static inline struct owl_clk_common * + hw_to_owl_clk_common(const struct clk_hw *hw) +{ + return container_of(hw, struct owl_clk_common, hw); +} + +int owl_clk_regmap_init(struct platform_device *pdev, + const struct owl_clk_desc *desc); +int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks); + +#endif /* _OWL_COMMON_H_ */