From patchwork Wed Jan 31 18:09:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126399 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp970799ljc; Wed, 31 Jan 2018 10:13:13 -0800 (PST) X-Google-Smtp-Source: AH8x224Ma2L5+WeUX9ZyF7YoSAxvE+RZtVaQHqY0gaQrtIi/qrLviicKki4INpz49YHALSC3JY4G X-Received: by 2002:a17:902:824:: with SMTP id 33-v6mr27756083plk.258.1517422393500; Wed, 31 Jan 2018 10:13:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517422393; cv=none; d=google.com; s=arc-20160816; b=iL0wnHEUbD6tE8g9oPXLpJW/z4AojWh1z9NjcqAW1rtpGyspxg401RGTCaRQenmHzD BkSl+/69+mSLGcjfMJgGQs2JOyTtcdbFcXdMXgogqtEB8kKQef5UoDxFi+l5mdiLg+1O +oFvhKq3h7ML5+gYlHM4aK8kF3YcKxVV2n5ry2WKXGE08kevQFplK/CsMX7gEjR6kgnL 5UnRgv5amHptU7EuHmdvhGRqqagmUw3oHuOKlpnN/GpeGFmx1rYVJ5v1DYNUnihAwVq7 ZE26RHkA1XriOlFGGbVtwBS7tEtWag6Tw+1Rr506je5/MPbxyNwcKcULArsgJ34eDoRC 55Wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Esh1w/6VF7E8mhZY77zdVBCnC+GGxNpxzEYVZAOjy0M=; b=Gc1nSVg0rJyEtM6E2o7c4LXPevJoO3fJLdYZqZdnq7HvCd+ch4yJJO/CAlmOS2Q+V9 607Q7GH0/hkwnN5LPCgYTkyzQXMgzZuSwWb5gKZ1Q/zHWtAZlKR8tGNCzzTI9RWeGf8Q KYfYGspNSXH/ChYBLgOQfWnnOXHfCoeINGw5vJtGr9AgsbUIZLfBtkUHXRx1pj4t8yde 2VrsrWmG/iHpxGVTIv+DL8Ghx5SgpK3Su4rZ8BNVTs4O59USKKDJHoUiM0lqAPWHgS79 mH675CyREznPb1MPwWmkzdEqahb1BO0YBbJ11BqzFzRHg3CrrUYoSu8Kbs9OO/CiQMY2 2IAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=T9YNKTag; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u19si2477700pfh.154.2018.01.31.10.13.13; Wed, 31 Jan 2018 10:13:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=T9YNKTag; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753926AbeAaSNL (ORCPT + 28 others); Wed, 31 Jan 2018 13:13:11 -0500 Received: from mail-wr0-f196.google.com ([209.85.128.196]:39184 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753741AbeAaSKB (ORCPT ); Wed, 31 Jan 2018 13:10:01 -0500 Received: by mail-wr0-f196.google.com with SMTP id f6so14388662wra.6 for ; Wed, 31 Jan 2018 10:10:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Esh1w/6VF7E8mhZY77zdVBCnC+GGxNpxzEYVZAOjy0M=; b=T9YNKTagiZsSCM1SgyAojrQzP5MuC0BJ81SMzY+VQ7KR7O8uOOb5w+RgxHeTvffl8a 2s1y4YYk5QpdjC9mb8iodBuCP3d8XxrqLLvuu2HZ1LqbO32A+eiWEmblXO9UqGV1JjXG 8xxhI/ZP9M+8fvuuLXFRsJSOjudWXpkfk8Q80KiyDw+h8+GQsqbGJamIQrpnqffN9Kmh nFzL+BBOZd7ZbplVhSIvg2p1weg+o3cU8pL6adtwwkgKqh5nTBs/QYFdZX4DFCCWhXsK +N84SOP6Ha5t93ESavjPd6lyf+mi5cwzCAUDNAW4fMK9yKiOuSxR85N00A85tzE/QeHF CWSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Esh1w/6VF7E8mhZY77zdVBCnC+GGxNpxzEYVZAOjy0M=; b=LOYB6YemK3BUky/fsfPIhhxPVEd3AuGKRRcx3h3wP+Uy/QSjkQyGx4N/RDXp/+kqWw uOqc4KqREif0pNUo2/Ocf2FXvu+lbWTmeXrQMxKOvnvoCodY2sWFaCxXxtKcAw2wc90r ojZCvDvE26JAU9raKy6gJ3z2y7Yc3P/FkY1NqUSw4sh3GciyjNEf9Rf+g1NVOdnrbo6j PmMFxjZHoutxlmkPpVHjbRYPTGYqgfQvdjhSHhxW78REIl787vwM+8zjZtWAJM3WON5e orKtUi4yrE/tR1/1JF1Rxkr/qZyX3YbODAz1mWb+mFqxnTA8VgYWk0keujK3p3sT0cqQ mTyA== X-Gm-Message-State: AKwxytcdhWd0JzGpLepbq2UKcxCfBWTkYtsZwJcfgUf+WiIdf1r/UCmf rliYdApnrH2Mu4Bcr/ZuXladgg== X-Received: by 10.223.196.216 with SMTP id o24mr15801577wrf.101.1517422200139; Wed, 31 Jan 2018 10:10:00 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id f8sm341977wmc.3.2018.01.31.10.09.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Jan 2018 10:09:59 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/19] clk: meson: migrate dividers to clk_regmap Date: Wed, 31 Jan 2018 19:09:36 +0100 Message-Id: <20180131180945.18025-11-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180131180945.18025-1-jbrunet@baylibre.com> References: <20180131180945.18025-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Move meson8b, gxbb and axg clocks using clk_divider to clk_regmap Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 61 ++++++------- drivers/clk/meson/gxbb.c | 217 ++++++++++++++++++++++---------------------- drivers/clk/meson/meson8b.c | 23 ++--- 3 files changed, 142 insertions(+), 159 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 3b7c970907c1..60b822d8905c 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -433,14 +433,15 @@ static struct clk_mux axg_mpeg_clk_sel = { }, }; -static struct clk_divider axg_mpeg_clk_div = { - .reg = (void *)HHI_MPEG_CLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, +static struct clk_regmap axg_mpeg_clk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_MPEG_CLK_CNTL, + .shift = 0, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "mpeg_clk_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "mpeg_clk_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -487,15 +488,16 @@ static struct clk_mux axg_sd_emmc_b_clk0_sel = { }, }; -static struct clk_divider axg_sd_emmc_b_clk0_div = { - .reg = (void *)HHI_SD_EMMC_CLK_CNTL, - .shift = 16, - .width = 7, - .lock = &meson_clk_lock, - .flags = CLK_DIVIDER_ROUND_CLOSEST, +static struct clk_regmap axg_sd_emmc_b_clk0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SD_EMMC_CLK_CNTL, + .shift = 16, + .width = 7, + .flags = CLK_DIVIDER_ROUND_CLOSEST, + }, .hw.init = &(struct clk_init_data) { .name = "sd_emmc_b_clk0_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -531,15 +533,16 @@ static struct clk_mux axg_sd_emmc_c_clk0_sel = { }, }; -static struct clk_divider axg_sd_emmc_c_clk0_div = { - .reg = (void *)HHI_NAND_CLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, - .flags = CLK_DIVIDER_ROUND_CLOSEST, +static struct clk_regmap axg_sd_emmc_c_clk0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_NAND_CLK_CNTL, + .shift = 0, + .width = 7, + .flags = CLK_DIVIDER_ROUND_CLOSEST, + }, .hw.init = &(struct clk_init_data) { .name = "sd_emmc_c_clk0_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -706,12 +709,6 @@ static struct clk_mux *const axg_clk_muxes[] = { &axg_sd_emmc_c_clk0_sel, }; -static struct clk_divider *const axg_clk_dividers[] = { - &axg_mpeg_clk_div, - &axg_sd_emmc_b_clk0_div, - &axg_sd_emmc_c_clk0_div, -}; - static struct clk_regmap *const axg_clk_regmaps[] = { &axg_clk81, &axg_ddr, @@ -760,6 +757,9 @@ static struct clk_regmap *const axg_clk_regmaps[] = { &axg_ao_i2c, &axg_sd_emmc_b_clk0, &axg_sd_emmc_c_clk0, + &axg_mpeg_clk_div, + &axg_sd_emmc_b_clk0_div, + &axg_sd_emmc_c_clk0_div, }; struct clkc_data { @@ -769,8 +769,6 @@ struct clkc_data { unsigned int clk_plls_count; struct clk_mux *const *clk_muxes; unsigned int clk_muxes_count; - struct clk_divider *const *clk_dividers; - unsigned int clk_dividers_count; struct clk_hw_onecell_data *hw_onecell_data; }; @@ -781,8 +779,6 @@ static const struct clkc_data axg_clkc_data = { .clk_plls_count = ARRAY_SIZE(axg_clk_plls), .clk_muxes = axg_clk_muxes, .clk_muxes_count = ARRAY_SIZE(axg_clk_muxes), - .clk_dividers = axg_clk_dividers, - .clk_dividers_count = ARRAY_SIZE(axg_clk_dividers), .hw_onecell_data = &axg_hw_onecell_data, }; @@ -838,11 +834,6 @@ static int axg_clkc_probe(struct platform_device *pdev) clkc_data->clk_muxes[i]->reg = clk_base + (u64)clkc_data->clk_muxes[i]->reg; - /* Populate base address for dividers */ - for (i = 0; i < clkc_data->clk_dividers_count; i++) - clkc_data->clk_dividers[i]->reg = clk_base + - (u64)clkc_data->clk_dividers[i]->reg; - /* Populate regmap for the regmap backed clocks */ for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++) axg_clk_regmaps[i]->map = map; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index ee1cd3785348..cdb20bf0682d 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -604,14 +604,15 @@ static struct clk_mux gxbb_mpeg_clk_sel = { }, }; -static struct clk_divider gxbb_mpeg_clk_div = { - .reg = (void *)HHI_MPEG_CLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_mpeg_clk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_MPEG_CLK_CNTL, + .shift = 0, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "mpeg_clk_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "mpeg_clk_sel" }, .num_parents = 1, .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), @@ -647,14 +648,15 @@ static struct clk_mux gxbb_sar_adc_clk_sel = { }, }; -static struct clk_divider gxbb_sar_adc_clk_div = { - .reg = (void *)HHI_SAR_CLK_CNTL, - .shift = 0, - .width = 8, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_sar_adc_clk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SAR_CLK_CNTL, + .shift = 0, + .width = 8, + }, .hw.init = &(struct clk_init_data){ .name = "sar_adc_clk_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "sar_adc_clk_sel" }, .num_parents = 1, }, @@ -705,14 +707,15 @@ static struct clk_mux gxbb_mali_0_sel = { }, }; -static struct clk_divider gxbb_mali_0_div = { - .reg = (void *)HHI_MALI_CLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_mali_0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_MALI_CLK_CNTL, + .shift = 0, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "mali_0_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "mali_0_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_NO_REPARENT, @@ -753,14 +756,15 @@ static struct clk_mux gxbb_mali_1_sel = { }, }; -static struct clk_divider gxbb_mali_1_div = { - .reg = (void *)HHI_MALI_CLK_CNTL, - .shift = 16, - .width = 7, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_mali_1_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_MALI_CLK_CNTL, + .shift = 16, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "mali_1_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "mali_1_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_NO_REPARENT, @@ -864,15 +868,16 @@ static struct clk_mux gxbb_cts_mclk_i958_sel = { }, }; -static struct clk_divider gxbb_cts_mclk_i958_div = { - .reg = (void *)HHI_AUD_CLK_CNTL2, - .shift = 16, - .width = 8, - .lock = &meson_clk_lock, - .flags = CLK_DIVIDER_ROUND_CLOSEST, +static struct clk_regmap gxbb_cts_mclk_i958_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_AUD_CLK_CNTL2, + .shift = 16, + .width = 8, + .flags = CLK_DIVIDER_ROUND_CLOSEST, + }, .hw.init = &(struct clk_init_data) { .name = "cts_mclk_i958_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "cts_mclk_i958_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -911,14 +916,15 @@ static struct clk_mux gxbb_cts_i958 = { }, }; -static struct clk_divider gxbb_32k_clk_div = { - .reg = (void *)HHI_32K_CLK_CNTL, - .shift = 0, - .width = 14, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_32k_clk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_32K_CLK_CNTL, + .shift = 0, + .width = 14, + }, .hw.init = &(struct clk_init_data){ .name = "32k_clk_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "32k_clk_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, @@ -983,15 +989,16 @@ static struct clk_mux gxbb_sd_emmc_a_clk0_sel = { }, }; -static struct clk_divider gxbb_sd_emmc_a_clk0_div = { - .reg = (void *)HHI_SD_EMMC_CLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, - .flags = CLK_DIVIDER_ROUND_CLOSEST, +static struct clk_regmap gxbb_sd_emmc_a_clk0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SD_EMMC_CLK_CNTL, + .shift = 0, + .width = 7, + .flags = CLK_DIVIDER_ROUND_CLOSEST, + }, .hw.init = &(struct clk_init_data) { .name = "sd_emmc_a_clk0_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1027,15 +1034,16 @@ static struct clk_mux gxbb_sd_emmc_b_clk0_sel = { }, }; -static struct clk_divider gxbb_sd_emmc_b_clk0_div = { - .reg = (void *)HHI_SD_EMMC_CLK_CNTL, - .shift = 16, - .width = 7, - .lock = &meson_clk_lock, - .flags = CLK_DIVIDER_ROUND_CLOSEST, +static struct clk_regmap gxbb_sd_emmc_b_clk0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SD_EMMC_CLK_CNTL, + .shift = 16, + .width = 7, + .flags = CLK_DIVIDER_ROUND_CLOSEST, + }, .hw.init = &(struct clk_init_data) { .name = "sd_emmc_b_clk0_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1071,15 +1079,16 @@ static struct clk_mux gxbb_sd_emmc_c_clk0_sel = { }, }; -static struct clk_divider gxbb_sd_emmc_c_clk0_div = { - .reg = (void *)HHI_NAND_CLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, - .flags = CLK_DIVIDER_ROUND_CLOSEST, +static struct clk_regmap gxbb_sd_emmc_c_clk0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_NAND_CLK_CNTL, + .shift = 0, + .width = 7, + .flags = CLK_DIVIDER_ROUND_CLOSEST, + }, .hw.init = &(struct clk_init_data) { .name = "sd_emmc_c_clk0_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1126,14 +1135,15 @@ static struct clk_mux gxbb_vpu_0_sel = { }, }; -static struct clk_divider gxbb_vpu_0_div = { - .reg = (void *)HHI_VPU_CLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_vpu_0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_VPU_CLK_CNTL, + .shift = 0, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "vpu_0_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "vpu_0_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1173,14 +1183,15 @@ static struct clk_mux gxbb_vpu_1_sel = { }, }; -static struct clk_divider gxbb_vpu_1_div = { - .reg = (void *)HHI_VPU_CLK_CNTL, - .shift = 16, - .width = 7, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_vpu_1_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_VPU_CLK_CNTL, + .shift = 16, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "vpu_1_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "vpu_1_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1245,14 +1256,15 @@ static struct clk_mux gxbb_vapb_0_sel = { }, }; -static struct clk_divider gxbb_vapb_0_div = { - .reg = (void *)HHI_VAPBCLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_vapb_0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_VAPBCLK_CNTL, + .shift = 0, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "vapb_0_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "vapb_0_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1292,14 +1304,15 @@ static struct clk_mux gxbb_vapb_1_sel = { }, }; -static struct clk_divider gxbb_vapb_1_div = { - .reg = (void *)HHI_VAPBCLK_CNTL, - .shift = 16, - .width = 7, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_vapb_1_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_VAPBCLK_CNTL, + .shift = 16, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "vapb_1_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "vapb_1_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1781,22 +1794,6 @@ static struct clk_mux *const gxbb_clk_muxes[] = { &gxbb_vapb_sel, }; -static struct clk_divider *const gxbb_clk_dividers[] = { - &gxbb_mpeg_clk_div, - &gxbb_sar_adc_clk_div, - &gxbb_mali_0_div, - &gxbb_mali_1_div, - &gxbb_cts_mclk_i958_div, - &gxbb_32k_clk_div, - &gxbb_sd_emmc_a_clk0_div, - &gxbb_sd_emmc_b_clk0_div, - &gxbb_sd_emmc_c_clk0_div, - &gxbb_vpu_0_div, - &gxbb_vpu_1_div, - &gxbb_vapb_0_div, - &gxbb_vapb_1_div, -}; - static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = { &gxbb_cts_amclk_div, }; @@ -1898,6 +1895,19 @@ static struct clk_regmap *const gx_clk_regmaps[] = { &gxbb_vapb_0, &gxbb_vapb_1, &gxbb_vapb, + &gxbb_mpeg_clk_div, + &gxbb_sar_adc_clk_div, + &gxbb_mali_0_div, + &gxbb_mali_1_div, + &gxbb_cts_mclk_i958_div, + &gxbb_32k_clk_div, + &gxbb_sd_emmc_a_clk0_div, + &gxbb_sd_emmc_b_clk0_div, + &gxbb_sd_emmc_c_clk0_div, + &gxbb_vpu_0_div, + &gxbb_vpu_1_div, + &gxbb_vapb_0_div, + &gxbb_vapb_1_div, }; struct clkc_data { @@ -1907,8 +1917,6 @@ struct clkc_data { unsigned int clk_plls_count; struct clk_mux *const *clk_muxes; unsigned int clk_muxes_count; - struct clk_divider *const *clk_dividers; - unsigned int clk_dividers_count; struct meson_clk_audio_divider *const *clk_audio_dividers; unsigned int clk_audio_dividers_count; struct clk_regmap *const *clk_regmaps; @@ -1923,8 +1931,6 @@ static const struct clkc_data gxbb_clkc_data = { .clk_plls_count = ARRAY_SIZE(gxbb_clk_plls), .clk_muxes = gxbb_clk_muxes, .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes), - .clk_dividers = gxbb_clk_dividers, - .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), .clk_audio_dividers = gxbb_audio_dividers, .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), .hw_onecell_data = &gxbb_hw_onecell_data, @@ -1937,8 +1943,6 @@ static const struct clkc_data gxl_clkc_data = { .clk_plls_count = ARRAY_SIZE(gxl_clk_plls), .clk_muxes = gxbb_clk_muxes, .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes), - .clk_dividers = gxbb_clk_dividers, - .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), .clk_audio_dividers = gxbb_audio_dividers, .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), .hw_onecell_data = &gxl_hw_onecell_data, @@ -1996,11 +2000,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev) clkc_data->clk_muxes[i]->reg = clk_base + (u64)clkc_data->clk_muxes[i]->reg; - /* Populate base address for dividers */ - for (i = 0; i < clkc_data->clk_dividers_count; i++) - clkc_data->clk_dividers[i]->reg = clk_base + - (u64)clkc_data->clk_dividers[i]->reg; - /* Populate base address for the audio dividers */ for (i = 0; i < clkc_data->clk_audio_dividers_count; i++) clkc_data->clk_audio_dividers[i]->base = clk_base; diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 835dbb1d2c9d..e9c5278072cd 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -393,14 +393,15 @@ struct clk_mux meson8b_mpeg_clk_sel = { }, }; -struct clk_divider meson8b_mpeg_clk_div = { - .reg = (void *)HHI_MPEG_CLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, +struct clk_regmap meson8b_mpeg_clk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_MPEG_CLK_CNTL, + .shift = 0, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "mpeg_clk_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "mpeg_clk_sel" }, .num_parents = 1, .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), @@ -623,10 +624,6 @@ static struct clk_mux *const meson8b_clk_muxes[] = { &meson8b_mpeg_clk_sel, }; -static struct clk_divider *const meson8b_clk_dividers[] = { - &meson8b_mpeg_clk_div, -}; - static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_clk81, &meson8b_ddr, @@ -706,6 +703,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_ao_ahb_sram, &meson8b_ao_ahb_bus, &meson8b_ao_iface, + &meson8b_mpeg_clk_div, }; static const struct meson8b_clk_reset_line { @@ -844,11 +842,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev) meson8b_clk_muxes[i]->reg = clk_base + (u32)meson8b_clk_muxes[i]->reg; - /* Populate base address for dividers */ - for (i = 0; i < ARRAY_SIZE(meson8b_clk_dividers); i++) - meson8b_clk_dividers[i]->reg = clk_base + - (u32)meson8b_clk_dividers[i]->reg; - /* Populate regmap for the regmap backed clocks */ for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++) meson8b_clk_regmaps[i]->map = map;