From patchwork Fri Jan 19 15:55:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 125182 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp352306ljf; Fri, 19 Jan 2018 07:56:59 -0800 (PST) X-Google-Smtp-Source: ACJfBotujo0Pidx0hcgaGDpoMJUvE+3sX6WyN5ZfpTov0+MxNMdyB37XiIr50AOK4CMhvtmzLIQU X-Received: by 10.101.81.7 with SMTP id f7mr41783157pgq.425.1516377419441; Fri, 19 Jan 2018 07:56:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516377419; cv=none; d=google.com; s=arc-20160816; b=vpHs9SOyBgMnk4iZZ0Rxd5+xXZw5S3DAKx72GQDtnyBfNchtC4uauV3mPHzXZsvifE eDop9V5vIkZHB3JGRVP/wghTukKI2dQOxUqE2fTblDNfgOHfonEoaEnu770PeyBbf1o2 d0aqujpfOYZwgcvH7kKD+wHZ0+w36JiZqhx8mH1C/SpOSa8+lBkckad1ETHUtCGPmrui h8grUYwdyOZsqqFEE4Y5H9bpeJPRwkvrH1yTgMaUkTq1sqPaLFj/zwe06ca6Y49/u1dq 5KGncg96UmQYl3Le5OZPB0GPclsRXt92FKkPcGVV0LS/W4w6jfE+sSGdWzwSRLMaL71I rZKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=HQTgarqjlANMQukbmqKWWWvuUu+aJX6Noc9V1rcWPJM=; b=D9Jes9jrKQf1vVOaInXLG0j11GONAvxDNUWbWqUsYtsYWD4zGbX4jtJbtpJz/TvwFF 4Y/FhGdtI6t+oIHqanedwZuD2PWVjt6l2tMDGOgT6Eof2tkaSbeHvzKQ+KWkbjKjX7zg nO68qXoZAreyouoW0cCxOF7rVCngO0Vilg1eBYj2XPdk0N8yJir3cOKsKWKpomYDJUa/ kAziMulLHkhIpW/2Re47oZ+bKeagsnGjDaJ0LZQp+m0ljbHRAr2LrlIRo+WqaS6Nn/1W ljpe1oU2TCj8xlb44fm/UXwaOceB+SdltQ8gW2ZyLVnj4HiKnkIDMc1ovbk25cOZAqKx 2sfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=KVbgc74X; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s15si8447989pgf.99.2018.01.19.07.56.59; Fri, 19 Jan 2018 07:56:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=KVbgc74X; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755787AbeASP4l (ORCPT + 28 others); Fri, 19 Jan 2018 10:56:41 -0500 Received: from mail-wr0-f196.google.com ([209.85.128.196]:38147 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755923AbeASPzj (ORCPT ); Fri, 19 Jan 2018 10:55:39 -0500 Received: by mail-wr0-f196.google.com with SMTP id x1so1986693wrb.5 for ; Fri, 19 Jan 2018 07:55:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HQTgarqjlANMQukbmqKWWWvuUu+aJX6Noc9V1rcWPJM=; b=KVbgc74XnaYiwx1Da38qRnu/R/JcjLW16WgFSSBDvZcFJ+pllHMvq1cYjY8oBfYrOa +Oih944tkmKKThlMHDGzAN8hu+gd3YnqAcec14EfoaqUMGDmr6AWwUlGcFntdxNnUVxw 97tX5kgANgMWwhRIMTdDlSbtqkOddEa4ITC909vevx0mE5+6EWRWE29StnUJsQBtG+ZQ KHif2w+C8qtsF5d2OyZdvhl48IUnUoFvRJyUx6/RxiXRpkH/oAtyhoxlnbFc7LYvdm18 oK5XtKAdzZ1+bhlsM4eZcbLxaBNI/9HSZuQ97Ni+JvhEp86dhnz+OcWULyVMWQXB5Ze1 J0Yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HQTgarqjlANMQukbmqKWWWvuUu+aJX6Noc9V1rcWPJM=; b=Dp94GchwWSxW04NWOlfWcnHnfOGfJzw38YnV86oNZ1mUGSvv7BdX/gxuNatIwZAEwe WwF08homGDrtvXI2jpty6ACNzQKKceJzmWoF8MNzWMtH3LpvYHHo646Xet78V+Y7OOWP rZaXPm7oMC37oMt6SkfnF/JHSFONcmhQXcV1fbLIeLOUcypJ+v8szTiLNEnuXKGVMU2a AOHRimdV1nFsEv5n5wL/BDwT0kUD01arQDk3o5PQoJbOZ0MfdjMP8lfBvukvfqCM4bOU lmxNfxkLS7zpa9anElKG0ubDvq8tesGR2Ifsz9D/ZviHiAABT+X8UiLXpOxbokKQkh00 S7uQ== X-Gm-Message-State: AKwxyte/OPVY7lwQJwLw/GBuoaRCcQr1jLkDluDnLyyxqUSwhcLUfWSq zRk4wIOEvhk4DIgeWahym/9fKg== X-Received: by 10.223.183.23 with SMTP id l23mr10195874wre.33.1516377338619; Fri, 19 Jan 2018 07:55:38 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id w73sm25883027wrb.34.2018.01.19.07.55.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 19 Jan 2018 07:55:38 -0800 (PST) From: Jerome Brunet To: Neil Armstrong Cc: Jerome Brunet , Kevin Hilman , Carlo Caione , Michael Turquette , Stephen Boyd , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/9] clk: meson: add the gxl hdmi pll Date: Fri, 19 Jan 2018 16:55:26 +0100 Message-Id: <20180119155529.11532-7-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119155529.11532-1-jbrunet@baylibre.com> References: <20180119155529.11532-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The hdmi pll used in the gxl family is actually different from the gxbb one. The register layout is completely different, which explain why the hdmi pll rate has always been rubbish on the gxl family. Adding the correct register field is the first part of the fix to get a correct rate out the hdmi pll Fixes: 0d48fc558d01 ("clk: meson-gxbb: Add GXL/GXM GP0 Variant") Signed-off-by: Jerome Brunet --- drivers/clk/meson/gxbb.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index cf083a1906d1..f74ed52e2673 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -253,6 +253,52 @@ static struct meson_clk_pll gxbb_hdmi_pll = { }, }; +static struct meson_clk_pll gxl_hdmi_pll = { + .m = { + .reg_off = HHI_HDMI_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_HDMI_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .frac = { + /* + * On gxl, there is a register shift due to HHI_HDMI_PLL_CNTL1 + * which does not exist on gxbb, so we compute the register + * offset based on the PLL base to get it right + */ + .reg_off = HHI_HDMI_PLL_CNTL + 4, + .shift = 0, + .width = 12, + }, + .od = { + .reg_off = HHI_HDMI_PLL_CNTL + 8, + .shift = 21, + .width = 2, + }, + .od2 = { + .reg_off = HHI_HDMI_PLL_CNTL + 8, + .shift = 23, + .width = 2, + }, + .od3 = { + .reg_off = HHI_HDMI_PLL_CNTL + 8, + .shift = 19, + .width = 2, + }, + .lock = &meson_clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "hdmi_pll", + .ops = &meson_clk_pll_ro_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + static struct meson_clk_pll gxbb_sys_pll = { .m = { .reg_off = HHI_SYS_PLL_CNTL, @@ -1520,7 +1566,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = { static struct clk_hw_onecell_data gxl_hw_onecell_data = { .hws = { [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, - [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, + [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw, [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, @@ -1675,7 +1721,7 @@ static struct meson_clk_pll *const gxbb_clk_plls[] = { static struct meson_clk_pll *const gxl_clk_plls[] = { &gxbb_fixed_pll, - &gxbb_hdmi_pll, + &gxl_hdmi_pll, &gxbb_sys_pll, &gxl_gp0_pll, };