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[209.132.180.67]) by mx.google.com with ESMTP id s15si8447989pgf.99.2018.01.19.07.57.11; Fri, 19 Jan 2018 07:57:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=1nRkJbPO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932362AbeASP5I (ORCPT + 28 others); Fri, 19 Jan 2018 10:57:08 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:37636 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755880AbeASPzj (ORCPT ); Fri, 19 Jan 2018 10:55:39 -0500 Received: by mail-wm0-f65.google.com with SMTP id v71so4484890wmv.2 for ; Fri, 19 Jan 2018 07:55:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bI4DgYc7fpUGm7XLj3iuDgsxinfuVyLuBA5IPYvWkK8=; b=1nRkJbPO5a/uEuYSPbkEW3cV1W5fHte4siSbA8PRR7c1xLqpU8iFg4n4nmLrmXeJnT 4h6xzU8lkoPfj6I3Sy/m4JVuc5bGhIw7i0QGoLEZDVej2fcWxs0MjVL0skY7WB7GhYIU EdkmzJ1Pc404Yjv2OcHSeodtNCXAQsQ3JZlAA1nrlfGw8UR84uat4Umv+EzsRmZ7hiM4 2kXhElk4cT1Hz1KzC6p87QsCzAtpbHe2VxnypAQ3QqyFWSrZdQTe+mIwDG9m10RBFmp4 N2a+BFKIMFfUBLVI4e34nLjKHn816RRwAJWZrMjkOe4Efk3GNgVubjtiKtu7Sl83+kmy rzYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bI4DgYc7fpUGm7XLj3iuDgsxinfuVyLuBA5IPYvWkK8=; b=RPdTvhHulMkaQgEVISaWvSkEYbkvVjlmZHXUv+MrJ/RbMI67iTT5e1hzYemm8+71eI vGpTyM6geKl+4U75v0hMwuJ39MDQus5XEPyDaoPVpTAAt+xgd4gxHu/4EV7jl2YNoM3P ydF3MEO7UFWtKsGUeQTuvFZVdMC/ORQIQUrRkKSfDG2cq2EC2hLlNlqRuzxERZKhlHiM jPCByj0RJAAKXedyNHy6XIqrTtytOUhStue3MXx6B80XQM6XWiZyV0g9UhMO5I3xPoAk 8nYw/FqLN/Yf9qb424Bx4OpgK2oXJKAs7llsk2qxZ4Lbd9slB44E1V/bl/uQgY17L9lF tORQ== X-Gm-Message-State: AKwxytfRnVCyADqZ976+u+xjiZ4s40/Cm9bbPv2ZHAms+dut2QfiQCf5 ovVmBp5qkbn41MZHhPZnwuvYXA== X-Received: by 10.28.169.200 with SMTP id s191mr8770576wme.9.1516377337609; Fri, 19 Jan 2018 07:55:37 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id w73sm25883027wrb.34.2018.01.19.07.55.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 19 Jan 2018 07:55:36 -0800 (PST) From: Jerome Brunet To: Neil Armstrong Cc: Jerome Brunet , Kevin Hilman , Carlo Caione , Michael Turquette , Stephen Boyd , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/9] clk: meson: add od3 to the pll driver Date: Fri, 19 Jan 2018 16:55:25 +0100 Message-Id: <20180119155529.11532-6-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119155529.11532-1-jbrunet@baylibre.com> References: <20180119155529.11532-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some meson plls, such as the hdmi pll, are using a 3rd od parameter, which is yet another "power of 2" post divider. Add it to fix the calculation of the hdmi_pll rate Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") Signed-off-by: Jerome Brunet --- drivers/clk/meson/clk-pll.c | 19 ++++++++++++++++--- drivers/clk/meson/clkc.h | 2 ++ drivers/clk/meson/gxbb.c | 5 +++++ 3 files changed, 23 insertions(+), 3 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 50923d004d96..1595f02f610f 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -53,7 +53,7 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, struct meson_clk_pll *pll = to_meson_clk_pll(hw); struct parm *p; u64 rate; - u16 n, m, frac = 0, od, od2 = 0; + u16 n, m, frac = 0, od, od2 = 0, od3 = 0; u32 reg; p = &pll->n; @@ -74,7 +74,13 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, od2 = PARM_GET(p->width, p->shift, reg); } - rate = (u64)parent_rate * m; + p = &pll->od3; + if (p->width) { + reg = readl(pll->base + p->reg_off); + od3 = PARM_GET(p->width, p->shift, reg); + } + + rate = (u64)m * parent_rate; p = &pll->frac; if (p->width) { @@ -85,7 +91,7 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, rate *= 2; } - return div_u64(rate, n) >> od >> od2; + return div_u64(rate, n) >> od >> od2 >> od3; } static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, @@ -226,6 +232,13 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, writel(reg, pll->base + p->reg_off); } + p = &pll->od3; + if (p->width) { + reg = readl(pll->base + p->reg_off); + reg = PARM_SET(p->width, p->shift, reg, rate_set->od3); + writel(reg, pll->base + p->reg_off); + } + p = &pll->frac; if (p->width) { reg = readl(pll->base + p->reg_off); diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index c2ff0520ce53..4acb35bda669 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -41,6 +41,7 @@ struct pll_rate_table { u16 n; u16 od; u16 od2; + u16 od3; u16 frac; }; @@ -92,6 +93,7 @@ struct meson_clk_pll { struct parm frac; struct parm od; struct parm od2; + struct parm od3; const struct pll_setup_params params; const struct pll_rate_table *rate_table; unsigned int rate_count; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 2d851bad13fa..cf083a1906d1 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -238,6 +238,11 @@ static struct meson_clk_pll gxbb_hdmi_pll = { .shift = 22, .width = 2, }, + .od3 = { + .reg_off = HHI_HDMI_PLL_CNTL2, + .shift = 18, + .width = 2, + }, .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "hdmi_pll",