From patchwork Thu Jan 18 18:45:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 125008 Delivered-To: patch@linaro.org Received: by 10.46.64.27 with SMTP id n27csp247448lja; Thu, 18 Jan 2018 10:46:28 -0800 (PST) X-Google-Smtp-Source: ACJfBosFwYJO0KBr7KSx9pqmXQB31WtoBeBKhhawLXDmiv0WTocx1J3kwE1Bm6Xlyn9c4J2EcVq8 X-Received: by 10.98.158.89 with SMTP id s86mr23643661pfd.203.1516301188426; Thu, 18 Jan 2018 10:46:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516301188; cv=none; d=google.com; s=arc-20160816; b=vVx9jdFtfFUTc2ZtAVZzpWLWInVVMDsk+7uKvHL17R5BMNdPm5iZj+RUHDke5eF/RA 0ahW7xit0Fw26Tg4zhbuxJp/9wytqohDEO7x08HKbAoE5vf8N5G/mQRGDfW+KVQtM4lu Cpg868hG752Fozu9m9/FmAWQtrFiUsKPKwP04+Nojgy4kr2nbf6ke/QYDVwIt/8caLNZ EVaBrsOm0JkPnI2NMBhPxd3D/M3wySt1MUB3G0E0CPoM0HWosSwUu4FQTImxpjnNoV34 2LV2SESv2Zcx69nlx5ixuksp678/aUyuMLg405WR0VfRHKVP5oLiQJdHuxe/aH1MmHO0 pNkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=aUsyxn3qKCQaAo3rtTr/Nydn9rZtVI7+J9ltTUWN6XA=; b=irb8UbI7kkjPkrnRKuOn0cvZdGW3U4BwF9LjlkzdwDqzoqwVrCqqJiZRQXleLTzCco KZlqujhHnPGIuNJuvWOom8RdMDiyjPB43Kja6Gq4/9iJp4Sacz2AZXNhldjLhueMdaU9 SnI0BMXiUCNFaA3ZBAH7fqX3nfsH+T3YTkT3yypDLY5/TVPHP7KO+4o2b3h1IOCpVv85 MwRaWi7muF+iew99HrQRnggSLpHdfTY0OCuy7tQjEzSZTHZwVcH5SGhxzSdEWKCzfbhi 0nayiCql61y4eLA/H6nCacWurKfJb6qZkzrpJ7R6sK9EPX8Xxl5q7b3PFzbQq08Qdafp 4X1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=l4NJhsGm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s17si6624629pge.525.2018.01.18.10.46.28; Thu, 18 Jan 2018 10:46:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=l4NJhsGm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756096AbeARSq0 (ORCPT + 28 others); Thu, 18 Jan 2018 13:46:26 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:46779 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755842AbeARSpl (ORCPT ); Thu, 18 Jan 2018 13:45:41 -0500 Received: by mail-wr0-f195.google.com with SMTP id g21so23597196wrb.13 for ; Thu, 18 Jan 2018 10:45:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aUsyxn3qKCQaAo3rtTr/Nydn9rZtVI7+J9ltTUWN6XA=; b=l4NJhsGmggWKt7iLzvmwng/mCnXLejLFkhfIs+JYOlXi8/s/HNdOQLxIZPjxqquo21 lcg890kLdZ6hu5tXveu4P2E1ZqBSofo238QCavWCzk8eworcsv1aweAEo+so4j5lT0TJ +vGrxEs7RVzmCQkGRY/n7HkM3CStFgkGcI7KuzDUWkxuyZ6A9/5zweb34LieB9MkKP0g VRXORLnsvFBeENwYIIi4d4PVEDlw8jaQJQ2LKPW+5PNmqiZOiGvIjp7rW8jW0a4omVpf zJTI33MMLX7Kq2zc2blahpULcBBinIkti60P0oW0oOCcLl7hDtJ0OnlG9n5hGL3L8cWz /YXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aUsyxn3qKCQaAo3rtTr/Nydn9rZtVI7+J9ltTUWN6XA=; b=YvNe+H6wKqGKa4wzBTuOaJjdTMSwLrIq+wBP1cMNIeik1NIHRfh2Ctsuphssc7ueon AN/B6SyOx4yC05IbDuM9qmtIAtNYGklksGg19sFg8OhHJosVYra59/xCM3O402JtV0Jh WCywzrnlB92BIJOiWoxbWhatLXLI6vZgtVIAQMFYIO5BmByq81Ix2/nIh4A17FImm3gS He135pgigLLlshBc1qbcjy9rrLMQ1ntRfHX6GzBCUxVYsSswEo35GVkunaBb2MKuWpzI qyK3+F+cl0lwqBohWUy/n4C1vDVOu3wMl6pcycypFx7QIz/fv7XQfeLGyr/7IeTpG9FI ivYw== X-Gm-Message-State: AKwxytdYAPqZHXGguMLiEoR0FN2411tHSi9n49AZ1R++DP7DP0XuW6aJ gFrF5ot2Yd6J95W6v2qZd86Q0A== X-Received: by 10.223.135.2 with SMTP id a2mr6787684wra.126.1516301140678; Thu, 18 Jan 2018 10:45:40 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id y62sm6240236wrb.48.2018.01.18.10.45.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 10:45:40 -0800 (PST) From: Jerome Brunet To: Neil Armstrong Cc: Jerome Brunet , Kevin Hilman , Carlo Caione , Michael Turquette , Stephen Boyd , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/9] clk: meson: add gxl hdmi pll Date: Thu, 18 Jan 2018 19:45:29 +0100 Message-Id: <20180118184532.6856-7-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180118184532.6856-1-jbrunet@baylibre.com> References: <20180118184532.6856-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The hdmi pll used in the gxl family is actually different from the gxbb. The register layout is completely different, which explain why the hdmi pll rate has always been rubbish on the gxl. Adding the correct register field is the first part of the fix to get a correct rate out the hdmi pll Fixes: 0d48fc558d01 ("clk: meson-gxbb: Add GXL/GXM GP0 Variant") Signed-off-by: Jerome Brunet --- drivers/clk/meson/gxbb.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index cf083a1906d1..08b3e1cdba5b 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -253,6 +253,52 @@ static struct meson_clk_pll gxbb_hdmi_pll = { }, }; +static struct meson_clk_pll gxl_hdmi_pll = { + .m = { + .reg_off = HHI_HDMI_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_HDMI_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .frac = { + /* + * On gxl, there a register shift due to HHI_HDMI_PLL_CNTL1 + * which does not exist on gxbb, so we compute the register + * offset based on the PLL base to get it right + */ + .reg_off = HHI_HDMI_PLL_CNTL + 4, + .shift = 0, + .width = 12, + }, + .od = { + .reg_off = HHI_HDMI_PLL_CNTL + 8, + .shift = 21, + .width = 2, + }, + .od2 = { + .reg_off = HHI_HDMI_PLL_CNTL + 8, + .shift = 23, + .width = 2, + }, + .od3 = { + .reg_off = HHI_HDMI_PLL_CNTL + 8, + .shift = 19, + .width = 2, + }, + .lock = &meson_clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "hdmi_pll", + .ops = &meson_clk_pll_ro_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + static struct meson_clk_pll gxbb_sys_pll = { .m = { .reg_off = HHI_SYS_PLL_CNTL, @@ -1520,7 +1566,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = { static struct clk_hw_onecell_data gxl_hw_onecell_data = { .hws = { [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, - [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, + [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw, [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, @@ -1675,7 +1721,7 @@ static struct meson_clk_pll *const gxbb_clk_plls[] = { static struct meson_clk_pll *const gxl_clk_plls[] = { &gxbb_fixed_pll, - &gxbb_hdmi_pll, + &gxl_hdmi_pll, &gxbb_sys_pll, &gxl_gp0_pll, };