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[209.132.180.67]) by mx.google.com with ESMTP id a11-v6si113495plt.567.2018.01.18.10.45.46; Thu, 18 Jan 2018 10:45:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=OF/6tvUt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932690AbeARSpo (ORCPT + 28 others); Thu, 18 Jan 2018 13:45:44 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:37875 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755821AbeARSpl (ORCPT ); Thu, 18 Jan 2018 13:45:41 -0500 Received: by mail-wm0-f65.google.com with SMTP id v71so24990397wmv.2 for ; Thu, 18 Jan 2018 10:45:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=P4HFAmqGPAwUfw5JwPEhd4HxAn9UU2y38qwTSMN6woQ=; b=OF/6tvUtLoNdHPCqw0KbU2t9DDBO0ll6DMfTukOEJh4nfPQP4XPu8bTt4r6IRpdly7 Ri+rW8ixRYNVa4LAN4rK+VoGWgbAdNK+VM32DiUQntoNR+1uszA4cpq4bO0lem/9E+mx lCCq8x7fu+dqgtSrue13k308UHZs8zpBMa8zw+W2vC8fS+Q5qqTnx8gWzsOW4rS7UY9H Ivicj2fmyAHJgp/yB+3jqoLNWK3E0Z7UxAw9Wi1L8/Hs8MFsQEAvYOZ0UNAtw/4MJ90+ tJw2lPx5tzxG241YdftanC4lKjX4haD2sYwIB0Xu4C+8UG/peTXxiCkwlTc/ay6TleV3 9laQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=P4HFAmqGPAwUfw5JwPEhd4HxAn9UU2y38qwTSMN6woQ=; b=OhBfFzmKBpTg3D5pb/CadeADFIOAILNRULnTHEAe0z/UJunYnK4HWkmfP0k3f2KwlU csvGNW1QaynDgwtWg2AgDVVoPWXG3eCVnETjs6X2aOpPofKl9ILBhXw++J073lQRVKCG FCLnJLbgljvoSXo98kPWuZ8xu2MUBTJchj0BLCb6qFOw2RYAHTpt2Y/r7zIO50V7Uk8E QDC0oEdw4VZ9XprYNgOwvabMjlGSTwdklYSBk+VeeF5KxnCyypjSFoAPnhMbjzlEyEGv qTqCcHF0+ygBjW+eA05g/Y/5SVPKx1g4hlSnLrul7AFOj+1UiB+wMKi8szJZniN6S0Jb mi6g== X-Gm-Message-State: AKwxytcjF/iDan2njvoNFkY6bRagNUTOh1Ie4SoC2DWj2BXQEdhGaWsE 7gLbBsYvGerl0pqH4zMX5vSnxUuw X-Received: by 10.28.48.10 with SMTP id w10mr6118087wmw.93.1516301139794; Thu, 18 Jan 2018 10:45:39 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id y62sm6240236wrb.48.2018.01.18.10.45.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 10:45:39 -0800 (PST) From: Jerome Brunet To: Neil Armstrong Cc: Jerome Brunet , Kevin Hilman , Carlo Caione , Michael Turquette , Stephen Boyd , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/9] clk: meson: add od3 to the pll driver Date: Thu, 18 Jan 2018 19:45:28 +0100 Message-Id: <20180118184532.6856-6-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180118184532.6856-1-jbrunet@baylibre.com> References: <20180118184532.6856-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some meson plls, such as the hdmi pll, are using a 3rd od parameter, which is yet another "power of 2" post divider. Add it to fix the calculation of the hdmi_pll rate Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") Signed-off-by: Jerome Brunet --- drivers/clk/meson/clk-pll.c | 17 +++++++++++++++-- drivers/clk/meson/clkc.h | 2 ++ drivers/clk/meson/gxbb.c | 5 +++++ 3 files changed, 22 insertions(+), 2 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index d9efe725b7ad..3f560b2cd83b 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -52,7 +52,7 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, struct meson_clk_pll *pll = to_meson_clk_pll(hw); struct parm *p; u64 rate; - u16 n, m, frac = 0, od, od2 = 0; + u16 n, m, frac = 0, od, od2 = 0, od3 = 0; u32 reg; p = &pll->n; @@ -73,6 +73,12 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, od2 = PARM_GET(p->width, p->shift, reg); } + p = &pll->od3; + if (p->width) { + reg = readl(pll->base + p->reg_off); + od3 = PARM_GET(p->width, p->shift, reg); + } + rate = (u64)m * parent_rate; p = &pll->frac; @@ -84,7 +90,7 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, rate *= 2; } - return (rate / n) >> od >> od2; + return (rate / n) >> od >> od2 >> od3; } static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, @@ -225,6 +231,13 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, writel(reg, pll->base + p->reg_off); } + p = &pll->od3; + if (p->width) { + reg = readl(pll->base + p->reg_off); + reg = PARM_SET(p->width, p->shift, reg, rate_set->od3); + writel(reg, pll->base + p->reg_off); + } + p = &pll->frac; if (p->width) { reg = readl(pll->base + p->reg_off); diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index c2ff0520ce53..4acb35bda669 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -41,6 +41,7 @@ struct pll_rate_table { u16 n; u16 od; u16 od2; + u16 od3; u16 frac; }; @@ -92,6 +93,7 @@ struct meson_clk_pll { struct parm frac; struct parm od; struct parm od2; + struct parm od3; const struct pll_setup_params params; const struct pll_rate_table *rate_table; unsigned int rate_count; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 2d851bad13fa..cf083a1906d1 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -238,6 +238,11 @@ static struct meson_clk_pll gxbb_hdmi_pll = { .shift = 22, .width = 2, }, + .od3 = { + .reg_off = HHI_HDMI_PLL_CNTL2, + .shift = 18, + .width = 2, + }, .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "hdmi_pll",