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[209.132.180.67]) by mx.google.com with ESMTP id k8si23429097pln.310.2017.12.26.02.33.53; Tue, 26 Dec 2017 02:33:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GHr4CCGz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751596AbdLZKdu (ORCPT + 28 others); Tue, 26 Dec 2017 05:33:50 -0500 Received: from mail-wr0-f196.google.com ([209.85.128.196]:39313 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751119AbdLZKbJ (ORCPT ); Tue, 26 Dec 2017 05:31:09 -0500 Received: by mail-wr0-f196.google.com with SMTP id o101so5666428wrb.6 for ; Tue, 26 Dec 2017 02:31:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AbBcmMD3JcZ+dotMW8Cfk674GIJYl4wfVzfE5phVVuk=; b=GHr4CCGzvzrv9CqIa3XzctshWArv4KV7zg9uqijok63jNaSMuT+OvIE3OIROkGCZ0T uj16Z5L/jB0zLfYuzilYR5RO3k0YxEQP2qopAU2ms0IfYIrOPuHrrK3QFmK+Q5C2y7If tQ2V/u9xPDPzqknXEYmURhA30RRYcVFsiD1go= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AbBcmMD3JcZ+dotMW8Cfk674GIJYl4wfVzfE5phVVuk=; b=Bv3JObPh34zPpEunZNYtQRajKxLtfULhwoGNB7JlyHWtxNzpy0sQTdgqa6Xeac7Gfa JnhJxC29DEt/9TKistqnf0mXW27bmsnN6PfWPKGLzeXhWYiDK9wujvMeLqT/RrhA4mfK OKED3mYpHzxL+jrK0hyu1vKUJHYaifqQY4qm5YxCyL1KgYpvliXNOs2P3O4GbLh2ZLPG HZ+CeODX2OWq9U4+uYPcJ8CIPGQASyHHQhpXfNai6sLzv37K16Yf9V5WomPcYAAYAW14 rhX/hBvWvTr/TNR8foS7iM6j3FWObTfT3Hr0lhitsmUDKpCnakZZiNn61DFe73RG/sj5 vq5Q== X-Gm-Message-State: AKGB3mKLL5YRCmbJazmRR5l8F9jfIFgKuXV5tbXcw3I1FvgANcZehioW PKoHIgjZsRlrKcizTWOifjWdUsqOnFg= X-Received: by 10.223.191.2 with SMTP id p2mr12335731wrh.81.1514284268350; Tue, 26 Dec 2017 02:31:08 -0800 (PST) Received: from localhost.localdomain ([160.171.216.245]) by smtp.gmail.com with ESMTPSA id l142sm13974036wmb.43.2017.12.26.02.31.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 Dec 2017 02:31:07 -0800 (PST) From: Ard Biesheuvel To: linux-kernel@vger.kernel.org Cc: Ard Biesheuvel , Dave Martin , Russell King - ARM Linux , Sebastian Andrzej Siewior , Mark Rutland , linux-rt-users@vger.kernel.org, Peter Zijlstra , Catalin Marinas , Will Deacon , Steven Rostedt , Thomas Gleixner Subject: [PATCH v4 10/20] arm64: assembler: add utility macros to push/pop stack frames Date: Tue, 26 Dec 2017 10:29:30 +0000 Message-Id: <20171226102940.26908-11-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171226102940.26908-1-ard.biesheuvel@linaro.org> References: <20171226102940.26908-1-ard.biesheuvel@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We are going to add code to all the NEON crypto routines that will turn them into non-leaf functions, so we need to manage the stack frames. To make this less tedious and error prone, add some macros that take the number of callee saved registers to preserve and the extra size to allocate in the stack frame (for locals) and emit the ldp/stp sequences. Signed-off-by: Ard Biesheuvel --- arch/arm64/include/asm/assembler.h | 57 ++++++++++++++++++++ 1 file changed, 57 insertions(+) -- 2.11.0 diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 8b168280976f..9130be742a32 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -499,6 +499,63 @@ alternative_else_nop_endif #endif .endm + /* + * frame_push - Push @regcount callee saved registers to the stack, + * starting at x19, as well as x29/x30, and set x29 to + * the new value of sp. Add @extra bytes of stack space + * for locals. + */ + .macro frame_push, regcount:req, extra + __frame st, \regcount, \extra + .endm + + /* + * frame_pop - Pop the callee saved registers from the stack that were + * pushed in the most recent call to frame_push, as well + * as x29/x30 and any extra stack space that may have been + * allocated. + */ + .macro frame_pop + __frame ld + .endm + + .macro __frame_regs, reg1, reg2, op, num + .if .Lframe_regcount == \num + \op\()r \reg1, [sp, #(\num + 1) * 8] + .elseif .Lframe_regcount > \num + \op\()p \reg1, \reg2, [sp, #(\num + 1) * 8] + .endif + .endm + + .macro __frame, op, regcount, extra=0 + .ifc \op, st + .if (\regcount) < 0 || (\regcount) > 10 + .error "regcount should be in the range [0 ... 10]" + .endif + .if ((\extra) % 16) != 0 + .error "extra should be a multiple of 16 bytes" + .endif + .set .Lframe_regcount, \regcount + .set .Lframe_extra, \extra + .set .Lframe_local_offset, ((\regcount + 3) / 2) * 16 + stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]! + mov x29, sp + .elseif .Lframe_regcount == -1 // && op == 'ld' + .error "frame_push/frame_pop may not be nested" + .endif + + __frame_regs x19, x20, \op, 1 + __frame_regs x21, x22, \op, 3 + __frame_regs x23, x24, \op, 5 + __frame_regs x25, x26, \op, 7 + __frame_regs x27, x28, \op, 9 + + .ifc \op, ld + ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra + .set .Lframe_regcount, -1 + .endif + .endm + /* * Errata workaround post TTBR0_EL1 update. */