From patchwork Fri Dec 22 02:45:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 122623 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1689198qgn; Thu, 21 Dec 2017 18:46:26 -0800 (PST) X-Google-Smtp-Source: ACJfBou6wpiVOrpFeu+O6XkXWKvREZ91HFLLInfQ/ccRsCHBt68J4nrAk1s8bbJ3z9N8dRd/K646 X-Received: by 10.84.193.129 with SMTP id f1mr12384630pld.363.1513910786101; Thu, 21 Dec 2017 18:46:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513910786; cv=none; d=google.com; s=arc-20160816; b=YpheC+WfDBsNYyHqDeCaPH4JlozbewdRV8FXY9f5fbccLPeKZiBYnrSkACdcaXGOVR SE3FFhEZnB1gf7+nmIkt/ZmUPkt3WM0s9LR7/zMwy10of3pqfJsoxOAj0hO8gktxi5Rl xQfBoMA9bqw2wD39avEwdMgXO/8fGMn9PZ/sNVpZL0Z5Ewo14zgubuIwo9Q9q0I6I3sl HNiB41Kw1+aAw/kzYoJGOyqoOo2qxZGCPuj7nozYoaNkG3bGzmEZxT8Or8mE0Ahi37mp 7vuQg1SkEvgE12HZDoUdlpma6szx0uPyQg6/y57a9VNOpwSZ1B2ZhQnj+fFkDYEupRac PBVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=NrEj55mGpzLhTGK9QtKdFfbqHQgeuIBipFHduLrbLek=; b=MokIxE+g8/Ak9RMFTkFnmN2SeDtv6BVZdQwkbm9JURpg2oSXFcrCaA9tHOFWDiaO3+ ab5XZjtvPrui+2d0gzqwu+VxXmZ5LWiD65jM8uEU2oOS3eeQqS8R1Ku5pJDQNyUVmmh6 s1lWNLPFkQiSx6P/6ZPHq9NmaYkNRCUpr6y5ueF+WtMzheGuynxLh/NbS+JO9RgjdAnN DkUrN5Gu668aSiDcBsXniTlgehkf5oA6KaZXw02HLGXYR4vWuihwaKz5t656GpaCb4Wa KLZO2iGbrKGopc1d1A9Ozan1sg73dXNx/rXDSuufB9NJydpIpzlsaRh13fVtUASKU/fx uHUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=DssmEsSb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d8si14599417pgu.56.2017.12.21.18.46.25; Thu, 21 Dec 2017 18:46:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=DssmEsSb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756087AbdLVCqS (ORCPT + 28 others); Thu, 21 Dec 2017 21:46:18 -0500 Received: from mail-pg0-f66.google.com ([74.125.83.66]:42700 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755893AbdLVCqH (ORCPT ); Thu, 21 Dec 2017 21:46:07 -0500 Received: by mail-pg0-f66.google.com with SMTP id q67so4778156pga.9; Thu, 21 Dec 2017 18:46:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=NrEj55mGpzLhTGK9QtKdFfbqHQgeuIBipFHduLrbLek=; b=DssmEsSbxvKWwA003VzpX++SqE/USrr2PRTSHHQh7I4Fn30GnMZvUTPH3VdJLLelZh U4fgNUN1aa1sKds1xKnFAGvvEaZ+tFFtT+OWBbmRozLMAmXmJ/kMX6fPDD0PIyFg5pdO lxjZuwpFzH7+2jn/O+Yv4JIo3q54ReRvH0d6qYLFm2yihq5ZASy+YLlq0Py57ojuLMBb pJ4GBk3CvXRL2xWzSa04aw6cm075l0gYgyoY9vFKK784lN80MAqoQk4zObORzZle+7FI DHN/pK0NuW6rhoLRcWnLQgSSWuNZdHiO+5tGhVH75MgMb3dy97+Ebw1clfFeVw6Ow8+7 /5xQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=NrEj55mGpzLhTGK9QtKdFfbqHQgeuIBipFHduLrbLek=; b=PoS8OLGKUaEZoGtG1+0gfFrPuzyi4T+T/0mT3U6UUsMAnTPxOxvxypdjcy4bkkCKjy 9fbRhCW6mZJ+Gdgyx4XjOCyaBz/rdBlwyHv7wUnY8adjOrLAVGuCBxh+O1gkUEjz1TtR 16BRcD9Sc486uO7NKp1b3BzSVK6Grx7mEnJJZancXX8tlYTPRXzCQbhOwdkU7dcZZ6/z tWEM9iFYNu0nyE6oNuPuYjDqIyWTSEDWduCZHrZJYj8EW2AJv9GL3h4c9pxsBPcUpEw+ VA9nxdQ3RsDvuaI8wk/OPqhJAfHYrdbMYblTScOjyCwpZj5Qh6y6UDdYfDg4RGEzjFlx rJnA== X-Gm-Message-State: AKGB3mK6zUyiP3hWpbK1/e4Q4cBQTjqmpqLYyjYtBz856bgCeW4d/agn 86vCA3YCglgz62nxPygS294= X-Received: by 10.99.127.29 with SMTP id a29mr11156958pgd.3.1513910766875; Thu, 21 Dec 2017 18:46:06 -0800 (PST) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id k14sm22200401pgt.48.2017.12.21.18.46.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Dec 2017 18:46:05 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Fri, 22 Dec 2017 13:15:57 +1030 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v7 3/5] clk: aspeed: Add platform driver and register PLLs Date: Fri, 22 Dec 2017 13:15:20 +1030 Message-Id: <20171222024522.10362-4-joel@jms.id.au> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171222024522.10362-1-joel@jms.id.au> References: <20171222024522.10362-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This registers a platform driver to set up all of the non-core clocks. The clocks that have configurable rates are now registered. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley -- v6: - Add Andrew's reviewed-by v5: - Remove eclk configuration. We do not have enough information to correctly implement the mux and divisor, so it will have to be implemented in the future v4: - Add eclk div table to fix ast2500 calculation - Add defines to document the BIT() macros - Pass dev where we can when registering clocks - Check for errors when registering clk_hws v3: - Fix bclk and eclk calculation - Separate out ast2400 and ast25000 for pll calculation --- drivers/clk/clk-aspeed.c | 130 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) -- 2.15.1 Reviewed-by: Benjamin Herrenschmidt diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 5adedda82d26..cf5ea63feb31 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -5,6 +5,8 @@ #include #include #include +#include +#include #include #include #include @@ -107,6 +109,18 @@ static const struct aspeed_gate_data aspeed_gates[] = { [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ }; +static const struct clk_div_table ast2500_mac_div_table[] = { + { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */ + { 0x1, 4 }, + { 0x2, 6 }, + { 0x3, 8 }, + { 0x4, 10 }, + { 0x5, 12 }, + { 0x6, 14 }, + { 0x7, 16 }, + { 0 } +}; + static const struct clk_div_table ast2400_div_table[] = { { 0x0, 2 }, { 0x1, 4 }, @@ -172,6 +186,122 @@ static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val) mult, div); } +struct aspeed_clk_soc_data { + const struct clk_div_table *div_table; + const struct clk_div_table *mac_div_table; + struct clk_hw *(*calc_pll)(const char *name, u32 val); +}; + +static const struct aspeed_clk_soc_data ast2500_data = { + .div_table = ast2500_div_table, + .mac_div_table = ast2500_mac_div_table, + .calc_pll = aspeed_ast2500_calc_pll, +}; + +static const struct aspeed_clk_soc_data ast2400_data = { + .div_table = ast2400_div_table, + .mac_div_table = ast2400_div_table, + .calc_pll = aspeed_ast2400_calc_pll, +}; + +static int aspeed_clk_probe(struct platform_device *pdev) +{ + const struct aspeed_clk_soc_data *soc_data; + struct device *dev = &pdev->dev; + struct regmap *map; + struct clk_hw *hw; + u32 val, rate; + + map = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(map)) { + dev_err(dev, "no syscon regmap\n"); + return PTR_ERR(map); + } + + /* SoC generations share common layouts but have different divisors */ + soc_data = of_device_get_match_data(dev); + if (!soc_data) { + dev_err(dev, "no match data for platform\n"); + return -EINVAL; + } + + /* UART clock div13 setting */ + regmap_read(map, ASPEED_MISC_CTRL, &val); + if (val & UART_DIV13_EN) + rate = 24000000 / 13; + else + rate = 24000000; + /* TODO: Find the parent data for the uart clock */ + hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_UART] = hw; + + /* + * Memory controller (M-PLL) PLL. This clock is configured by the + * bootloader, and is exposed to Linux as a read-only clock rate. + */ + regmap_read(map, ASPEED_MPLL_PARAM, &val); + hw = soc_data->calc_pll("mpll", val); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; + + /* SD/SDIO clock divider (TODO: There's a gate too) */ + hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, + soc_data->div_table, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw; + + /* MAC AHB bus clock divider */ + hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 16, 3, 0, + soc_data->mac_div_table, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; + + /* LPC Host (LHCLK) clock divider */ + hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, + soc_data->div_table, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw; + + /* P-Bus (BCLK) clock divider */ + hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0, + soc_data->div_table, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; + + return 0; +}; + +static const struct of_device_id aspeed_clk_dt_ids[] = { + { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data }, + { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data }, + { } +}; + +static struct platform_driver aspeed_clk_driver = { + .probe = aspeed_clk_probe, + .driver = { + .name = "aspeed-clk", + .of_match_table = aspeed_clk_dt_ids, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(aspeed_clk_driver); + static void __init aspeed_ast2400_cc(struct regmap *map) { struct clk_hw *hw;