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[209.132.180.67]) by mx.google.com with ESMTP id b61si10904799plc.277.2017.12.19.01.34.02; Tue, 19 Dec 2017 01:34:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=S9oMPkzh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S938966AbdLSJd4 (ORCPT + 28 others); Tue, 19 Dec 2017 04:33:56 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:57354 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S938905AbdLSJdx (ORCPT ); Tue, 19 Dec 2017 04:33:53 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBJ9W5bk012923; Tue, 19 Dec 2017 03:32:05 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513675926; bh=Euu2BSfh8tjrQfp8flGHV2W+OdC+6/SRofgdXGJY/y8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=S9oMPkzh2KUtTJhKRRC6zRC/UGUPb/TAQELfZxXC1hyytFxqrNXm+wZNpjTRffh/O 11gAY8g3ssCKeDPYJI7U1ubgCGT57tTUzNdeVUytyiTmVvICxTl9wrcSXHrr9uplfA sz5a1uCs3odVP+v54YFI7nESsWuNCi57wv2abk0k= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9W07t015740; Tue, 19 Dec 2017 03:32:00 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 19 Dec 2017 03:32:00 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 19 Dec 2017 03:32:00 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9VgHx012627; Tue, 19 Dec 2017 03:31:57 -0600 From: Kishon Vijay Abraham I To: Tony Lindgren , CC: Rob Herring , Mark Rutland , Russell King , , , , , , , Subject: [PATCH 4/7] ARM: dts: dra76-evm: Enable x2 PCIe lanes Date: Tue, 19 Dec 2017 15:01:30 +0530 Message-ID: <20171219093133.16565-5-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171219093133.16565-1-kishon@ti.com> References: <20171219093133.16565-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org DRA76 EVM has a 4-lane PCIe connector and DRA76 can support x2 lanes. Enable both the PCIe lanes here. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/dra76-evm.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index b024a65c6e27..244e553f2247 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -421,3 +421,19 @@ spi-max-frequency = <96000000>; }; }; + +&pcie2_phy { + status = "okay"; +}; + +&pcie1_rc { + num-lanes = <2>; + phys = <&pcie1_phy>, <&pcie2_phy>; + phy-names = "pcie-phy0", "pcie-phy1"; +}; + +&pcie1_ep { + num-lanes = <2>; + phys = <&pcie1_phy>, <&pcie2_phy>; + phy-names = "pcie-phy0", "pcie-phy1"; +};