From patchwork Thu Dec 14 13:40:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 121950 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6821745qgn; Thu, 14 Dec 2017 05:43:27 -0800 (PST) X-Google-Smtp-Source: ACJfBouaQbldDerlnG6R2p20o+A0Xbf6yAS149jcAxhXY9joyBQ4bHuBhFtw8eb6h/Oll2DCvlPq X-Received: by 10.98.18.88 with SMTP id a85mr9546699pfj.141.1513259007219; Thu, 14 Dec 2017 05:43:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513259007; cv=none; d=google.com; s=arc-20160816; b=E3E0avRxNMkteZjYm/Gtoc8cTnRFyHV4AOQdjzkG07xywqTDSrP1rHR5sODKAT80TG sMjTlk4Zto7NSaNZ2N26On/NwDMQLeKudrIYxOIQlz0YKl3xsZ7TcFqKX8RerWzUDbai YF4zpjhdjDFZ+RMmtuwHq9XNlW4RN5Q+G6/Uj79I3NmjSEE2pnzRL2+C4tovxpToCJ1c 9VKIriYycjJe8K1Mat7EQgDNfsms5q/U1lgG/GtucrIR40QLuasHsdYz3xEy4KJfH5qo uNAxAKuM9LfWD9YeRoz1oW1XTTkYdFer2pssJ6NU9vOBu8fOetR5jwwD2Ct1rZlRm3T7 f/NQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=d3Kc1N8mbkDKFu0TCeKjCyjCpiWN03Rt6l67FV0HmbU=; b=Jd8uVD7vAO0YqXaT14tyTuVe7LaxDMMLj00mTK6mwf9T/ooGWB/weim/tlJTzPZpnX x40jNecgOiATJnGbO8JyE8GbR771ZlRdl5piXGSfobdrgTemHBeKutoBbDU6wM/YoOf8 2QtQXPmA79JexhVJ2pOIxV3YXueRR1B9XYCrYd/AnQrc7+rOOmzobWOwaNIxA9UizDAh b5P4SDCKkI2WZ//ipQ+FWKqObJe0fqFV2X96hhb6VqLG/MzICnwDrXpE4PxFMttEqaIq KBq0zldx/8wBR2bIDpBmAn/vG3GSKRjU4RQBIBspl8rwNZ7Be7H3TX1ZQbETyKaATtvH Cmpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=km9arQk6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u131si2940937pgc.145.2017.12.14.05.43.26; Thu, 14 Dec 2017 05:43:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=km9arQk6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753071AbdLNNnY (ORCPT + 20 others); Thu, 14 Dec 2017 08:43:24 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:23237 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752483AbdLNNnU (ORCPT ); Thu, 14 Dec 2017 08:43:20 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBEDfR6V026839; Thu, 14 Dec 2017 07:41:27 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513258887; bh=3sM7hpddXUIUFt/ivB7gJaXdvctFMFxwrgsYYiHJ+UA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=km9arQk635AWOr2mvvfU3MSVOIg0sXYhx4gLzOPiwOZG5dSLwIW3WXDY8Y+3NgL1v 4n8cJMJgkR2dlXHaHeqaP84aVg8AuyzzO1LKEA+EbmD69R8psnoHnUaA/ghN1zv6AJ eo4InLyrhiXs3m6bKhEY1JxmnafKDHnbGvDLO/VU= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBEDfMj0002813; Thu, 14 Dec 2017 07:41:22 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 14 Dec 2017 07:41:22 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 14 Dec 2017 07:41:22 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBEDewBI009855; Thu, 14 Dec 2017 07:41:18 -0600 From: Kishon Vijay Abraham I To: Tony Lindgren , , Santosh Shilimkar CC: Rob Herring , Mark Rutland , Russell King , , , , , , , Subject: [PATCH 05/14] ARM: dts: dra76-evm: Shift to using common IOdelay data Date: Thu, 14 Dec 2017 19:10:45 +0530 Message-ID: <20171214134054.7749-6-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171214134054.7749-1-kishon@ti.com> References: <20171214134054.7749-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sekhar Nori Now that we have a device-tree include file with common MMC/SD IOdelay data for DRA76x SoC, shift the EVM device-tree file to using that. Tested-by: Jean-Jacques Hiblot Signed-off-by: Sekhar Nori Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra76-evm.dts | 41 +---------------------------------------- 1 file changed, 1 insertion(+), 40 deletions(-) -- 2.11.0 diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index b024a65c6e27..2770f6d3e1cb 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -9,6 +9,7 @@ #include "dra76x.dtsi" #include "dra7-evm-common.dtsi" +#include "dra76x-mmc-iodelay.dtsi" #include / { @@ -100,46 +101,6 @@ }; }; -&dra7_pmx_core { - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; -}; - &i2c1 { status = "okay"; clock-frequency = <400000>;