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[209.132.180.67]) by mx.google.com with ESMTP id k1si5294167plt.338.2017.12.08.03.33.45; Fri, 08 Dec 2017 03:33:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VzqE9Ok5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753601AbdLHLdm (ORCPT + 11 others); Fri, 8 Dec 2017 06:33:42 -0500 Received: from mail-wr0-f196.google.com ([209.85.128.196]:43839 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753439AbdLHLdT (ORCPT ); Fri, 8 Dec 2017 06:33:19 -0500 Received: by mail-wr0-f196.google.com with SMTP id z34so10499544wrz.10 for ; Fri, 08 Dec 2017 03:33:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uzXGlIzJcPCNtFot8pBV194scRWAkQS1wDTeXEtwM5A=; b=VzqE9Ok5JRjYtI9CedKCFJOlN3cfBooIX94OvWa6zRugUDAcalhT8lEEDI2TpyXS5J mp16COAcekXaKVW/mwkxtC5u0ch51IjJ9Li8hbcwzZYOLaBkAzaabjSy46GZCQfcqb6r RbqDow/cCrloMNNVKxmstg7DxBz18go+xMW8Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uzXGlIzJcPCNtFot8pBV194scRWAkQS1wDTeXEtwM5A=; b=pz21li8bvswyOTtpOrvsm5R3U083nnu2igzDZs0n85iRu7OT65dkjldhbFibEYEFHP i74isVkaCzF53AE2/aol3Sq8TJdqCVaF2FSbIVj3z8AP90BxJLpq9+FjqiuZTJRXwfMN ZVkNYHB+exc5oDfrDiL/01i3P1EiKMJYZUcHIcPoO2U1J/5ylzG57PBQznqmYsKEbIZn BCz9G92MJrJl2i6DnqLkQKc58u137pEOXxwBJtfpxKihjKQxDVhe8Ykargl4ISP342H9 il7V34La3w9Ffb3oDFpkPHmK1EY1VYttDnVcicbN8CUWLW8WDUQA4vSSUaMF3GzKJuTt BcGQ== X-Gm-Message-State: AJaThX4CxYQSj01SwxTNO/o9OgDiiiAot597bctYcjRiYzX10waJCvZ6 ru0Mv4/wn5DSXC7U/TjmWIUbMA== X-Received: by 10.223.193.135 with SMTP id x7mr27757051wre.211.1512732797326; Fri, 08 Dec 2017 03:33:17 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.241.46]) by smtp.gmail.com with ESMTPSA id x52sm9184518wrb.25.2017.12.08.03.33.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Dec 2017 03:33:16 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, arnd@arndb.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v9 6/6] arm: dts: stm32: remove useless clocksource nodes Date: Fri, 8 Dec 2017 12:32:50 +0100 Message-Id: <20171208113250.359-7-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171208113250.359-1-benjamin.gaignard@st.com> References: <20171208113250.359-1-benjamin.gaignard@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Benjamin Gaignard 16 bits timers aren't accurate enough to be used as clocksource, remove them from stm32f4 and stm32f7 devicetree. Signed-off-by: Benjamin Gaignard --- arch/arm/boot/dts/stm32f429.dtsi | 32 -------------------------------- arch/arm/boot/dts/stm32f746.dtsi | 32 -------------------------------- 2 files changed, 64 deletions(-) -- 2.15.0 diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 10099df8b73e..b507e04a52c6 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -107,14 +107,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -136,14 +128,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -193,14 +177,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -217,14 +193,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 5f66d151eedb..bb3e262bd456 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -103,14 +103,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -132,14 +124,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -189,14 +173,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -213,14 +189,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>;